A Power Efficient Multi-Bit Accelerator for Memory Prohibitive Deep Neural Networks. - Suhas Shivapakash; Hardik Jain; Olaf Hellwich; Friedel Gerfers (ISCAS, 2020)

A Power Efficiency Enhancements of a Multi-Bit Accelerator for Memory Prohibitive Deep Neural Networks. - Suhas Shivapakash; Hardik Jain; Olaf Hellwich; Friedel Gerfers (IEEE Open J. Circuits Syst., 2021)

FantastIC4: A Hardware-Software Co-Design Approach for Efficiently Running 4Bit-Compact Multilayer Perceptrons. - Simon Wiedemann; Suhas Shivapakash; Daniel Becking; Pablo Wiedemann; Wojciech Samek; Friedel Gerfers; Thomas Wiegand 001 (IEEE Open J. Circuits Syst., 2021)

Energy efficient hardware architectures for memory prohibitive deep neural networks. - Suhas Shivapakash (2024)