True single-phase energy-recovering logic for low-power, high-speed VLSI. - Suhwan Kim 001; Marios C. Papaefthymiou (ISLPED, 1998)

Single-phase source-coupled adiabatic logic. - Suhwan Kim 001; Marios C. Papaefthymiou (ISLPED, 1999)

Design, Verification, and Test of a True Single-Phase 8-bit Adiabatic Multiplier. - Suhwan Kim 001; Conrad H. Ziesler; Marios C. Papaefthymiou (ARVLSI, 2001)

A True Single-Phase 8-bit Adiabatic Multiplier. - Suhwan Kim 001; Conrad H. Ziesler; Marios C. Papaefthymiou (DAC, 2001)

A resonant clock generator for single-phase adiabatic systems. - Conrad H. Ziesler; Suhwan Kim 001; Marios C. Papaefthymiou (ISLPED, 2001)

True single-phase adiabatic circuitry. - Suhwan Kim 001; Marios C. Papaefthymiou (IEEE Trans. Very Large Scale Integr. Syst., 2001)

Multiplier architecture power consumption characterization for low-power DSP applications. - Sangjin Hong; Shu-Shin Chin; Suhwan Kim 001; Wei Hwang (ICECS, 2002)

Low-power Application-specific Parallel Array Multiplier Design for DSP Applications. - Sangjin Hong; Suhwan Kim 001; Wayne E. Stark (VLSI Design, 2002)

Minimizing inductive noise in system-on-a-chip with multiple power gating structures. - Suhwan Kim 001; Stephen V. Kosonocky; Daniel R. Knebel; Kevin Stawiasz; David F. Heidel; Michael Immediato (ESSCIRC, 2003)

Understanding and minimizing ground bounce during mode transition of power gating structures. - Suhwan Kim 001; Stephen V. Kosonocky; Daniel R. Knebel (ISLPED, 2003)

A clockless future for systems on chip. - Suhwan Kim 001; Conrad H. Ziesler (IEEE Des. Test Comput., 2003)

Fine-grain real-time reconfigurable pipelining. - Suhwan Kim 001; Conrad H. Ziesler; Marios C. Papaefthymiou (IBM J. Res. Dev., 2003)

Low-power circuits and technology for wireless digital systems. - Stephen V. Kosonocky; Azeez J. Bhavnagarwala; Kenneth Chin; George Gristede; Anne-Marie Haen; Wei Hwang; Mark B. Ketchen; Suhwan Kim 001; Daniel R. Knebel; Kevin W. Warren; Victor V. Zyuban (IBM J. Res. Dev., 2003)

Application of an SOI 0.12-µm CMOS technology to SoCs with low-power and high-frequency circuits. - Jean-Olivier Plouchart; Noah Zamdmer; Jonghae Kim; Melanie Sherony; Yue Tan; Asit Ray; Mohamed Talbi; Lawrence F. Wagner; Kun Wu; Naftali E. Lustig; Shreesh Narasimha; Patricia O'Neil; et al. (IBM J. Res. Dev., 2003)

A true single-phase energy-recovery multiplier. - Suhwan Kim 001; Conrad H. Ziesler; Marios C. Papaefthymiou (IEEE Trans. Very Large Scale Integr. Syst., 2003)

Experimental measurement of a novel power gating structure with intermediate power saving mode. - Suhwan Kim 001; Stephen V. Kosonocky; Daniel R. Knebel; Kevin Stawiasz (ISLPED, 2004)

Usage of Application-Specific Switching Activity for Energy Minimization of Arithmetic Units. - Shu-Shin Chin; Sangjin Hong; Suhwan Kim 001 (ISVLSI, 2004)

A synchronous interface for SoCs with multiple clock domains. - Visvesh S. Sathe 001; Conrad H. Ziesler; Marios C. Papaefthymiou; Suhwan Kim 001; Stephen V. Kosonocky (SoCC, 2004)

Power Reduction Technique in Coefficient Multiplications Through Multiplier Characterization. - Sangjin Hong; Shu-Shin Chin; Suhwan Kim 001; Wei Hwang (J. VLSI Signal Process., 2004)

Fast, efficient, recovering, and irreversible. - Visvesh S. Sathe 001; Juang-Ying Chueh; Joohee Kim; Conrad H. Ziesler; Suhwan Kim 001; Marios C. Papaefthymiou (Conf. Computing Frontiers, 2005)

Charge-Recovery Computing on Silicon. - Suhwan Kim 001; Conrad H. Ziesler; Marios C. Papaefthymiou (IEEE Trans. Computers, 2005)

A Storage- and Power-Efficient Range-Matching TCAM for Packet Classification. - Young-Deok Kim; Hyun-Seok Ahn; Joon-Young Park; Suhwan Kim 001; Deog-Kyoon Jeong (ISSCC, 2006)

A 2.8Gb/s All-Digital CDR with a 10b Monotonic DCO. - Do-Hwan Oh; Deok-Soo Kim; Suhwan Kim 001; Deog-Kyoon Jeong; Wonchan Kim (ISSCC, 2007)

A 0.25-µm CMOS 1.9-GHz PHS RF Transceiver With a 150-kHz Low-IF Architecture. - Hoesam Jeong; Byoung-Joo Yoo; Cheol Kyu Han; Sang-Yoon Lee 006; Kang-Yoon Lee; Suhwan Kim 001; Deog-Kyoon Jeong; Wonchan Kim (IEEE J. Solid State Circuits, 2007)

A Multi-Mode Power Gating Structure for Low-Voltage Deep-Submicron CMOS ICs. - Suhwan Kim 001; Stephen V. Kosonocky; Daniel R. Knebel; Kevin Stawiasz; Marios C. Papaefthymiou (IEEE Trans. Circuits Syst. II Express Briefs, 2007)

A high resolution capacitance deviation-to-digital converter utilizing time stretching. - Manho Kim; Nan Xing; Dong-Yong Shin; Hyunjoong Lee; Suhwan Kim 001 (SoCC, 2009)

A PVT-insensitive time-to-digital converter using fractional difference Vernier delay lines. - Nan Xing; Heesoo Song; Deog-Kyoon Jeong; Suhwan Kim 001 (SoCC, 2009)

A High-Speed Range-Matching TCAM for Storage-Efficient Packet Classification. - Young-Deok Kim; Hyun-Seok Ahn; Suhwan Kim 001; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

High-speed 10-bit LCD column driver with a split DAC and a class-AB output buffer. - Jong-Kwan Woo; Dong-Yong Shin; Deog-Kyoon Jeong; Suhwan Kim 001 (IEEE Trans. Consumer Electron., 2009)

A three-step power-gating turn-on technique for controlling ground bounce noise. - Rahul Singh; AhReum Kim; SoYoung Kim; Suhwan Kim 001 (ISLPED, 2010)

Footer voltage feedforward domino technique for wide fan-in dynamic logic. - Rahul Singh; AhReum Kim; Suhwan Kim 001 (SoCC, 2010)

A high-resolution and fast-conversion readout circuit for differential capacitive sensors. - Jong-Kwan Woo; Hyunjoong Lee; SungHo Ahn; Suhwan Kim 001 (SoCC, 2010)

A 0.3-1.4 GHz All-Digital Fractional-N PLL With Adaptive Loop Gain Controller. - Deok-Soo Kim; Heesoo Song; Taeho Kim; Suhwan Kim 001; Deog-Kyoon Jeong (IEEE J. Solid State Circuits, 2010)

Charge Amplifier With an Enhanced Frequency Response for SPM-Based Data Storage. - Hyunjoong Lee; Jong-Kwan Woo; Hyo-Jin Nam; Won-Hyeog Jin; Moongi Jeong; Young-Sik Kim; Jin-Koog Shin; Suhwan Kim 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

A 14.6 ps Resolution, 50 ns Input-Range Cyclic Time-to-Digital Converter Using Fractional Difference Conversion Method. - Nan Xing; Jong-Kwan Woo; Woo-Yeol Shin; Hyunjoong Lee; Suhwan Kim 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

A static-switching pulse domino technique for statistical power reduction of wide fan-in dynamic gates. - Rahul Singh; Jae-Cheol Son; Ukrae Cho; Gunok Jung; Min-Su Kim; Hyoungwook Lee; Suhwan Kim 001 (ACM Great Lakes Symposium on VLSI, 2011)

A low-power referenceless clock and data recovery circuit with clock-edge modulation for biomedical sensor applications. - Sunkwon Kim; Jong-Kwan Woo; Woo-Yeol Shin; Gi-Moon Hong; Hyongmin Lee; Hyunjoong Lee; Suhwan Kim 001 (ISLPED, 2011)

A CMOs readout integrated circuit with wide dynamic range for a CNT bio-sensor array system. - Hyunjoong Lee; Hyongmin Lee; Jong-Kwan Woo; Sunkwon Kim; Young June Park; Suhwan Kim 001 (ISLPED, 2011)

A comparator-based cyclic analog-to-digital converter with boosted preset voltage. - Jong-Kwan Woo; Tae-Hoon Kim; Hyongmin Lee; Sunkwon Kim; Hyunjoong Lee; Suhwan Kim 001 (ISLPED, 2011)

A 4.8Gb/s impedance-matched bidirectional multi-drop transceiver for high-capacity memory interface. - Woo-Yeol Shin; Gi-Moon Hong; Hyongmin Lee; Jaeduk Han; Sunkwon Kim; Kyu-Sang Park; Dong-Hyuk Lim; Jung-Hoon Chun; Deog-Kyoon Jeong; Suhwan Kim 001 (ISSCC, 2011)

A 1.0-4.0-Gb/s All-Digital CDR With 1.0-ps Period Resolution DCO and Adaptive Proportional Gain Control. - Heesoo Song; Deok-Soo Kim; Do-Hwan Oh; Suhwan Kim 001; Deog-Kyoon Jeong (IEEE J. Solid State Circuits, 2011)

A Low-Cost and Low-Power Time-to-Digital Converter Using Triple-Slope Time Stretching. - Manho Kim; Hyunjoong Lee; Jong-Kwan Woo; Nan Xing; Min-Oh Kim; Suhwan Kim 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2011)

A Delta-Sigma Interface Circuit for Capacitive Sensors With an Automatically Calibrated Zero Point. - Dong-Yong Shin; Hyunjoong Lee; Suhwan Kim 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2011)

Improving the Accuracy of Capacitance-to-Frequency Converter by Accumulating Residual Charges. - Dong-Yong Shin; Hyunjoong Lee; Suhwan Kim 001 (IEEE Trans. Instrum. Meas., 2011)

Neural recording system with low-noise analog front-end and comparator-based cyclic ADC. - Susie Kim; Seung-In Na; Tae-Hoon Kim; Hyunjoong Lee; Sunkwon Kim; Cyuyeol Rhee; Suhwan Kim 001 (SoCC, 2012)

Static-switching pulse domino: A switching-aware design technique for wide fan-in dynamic multiplexers. - Rahul Singh; Gi-Moon Hong; Mino Kim; Jihwan Park; Woo-Yeol Shin; Suhwan Kim 001 (Integr., 2012)

Integrating Metal-Oxide-Decorated CNT Networks with a CMOS Readout in a Gas Sensor. - Hyunjoong Lee; Sanghoon Lee; Dai-Hong Kim; David Perello; Young June Park; Seong-Hyeon Hong; Minhee Yun; Suhwan Kim 001 (Sensors, 2012)

Power-Gating Noise Minimization by Three-Step Wake-Up Partitioning. - Rahul Singh; Jong-Kwan Woo; Hyunjoong Lee; SoYoung Kim; Suhwan Kim 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

A 32-channel neural recording system with a liquid-crystal polymer MEA. - Seung-In Na; Susie Kim; Taehoon Kim; Hyongmin Lee; Hyunjoong Lee; Suhwan Kim 001 (BioCAS, 2013)

High-resolution and wide-dynamic range time-to-digital converter with a multi-phase cyclic Vernier delay line. - Mino Kim; Woo-Yeol Shin; Gi-Moon Hong; Jihwan Park; Joo-Hyung Chae; Nan Xing; Jong-Kwan Woo; Suhwan Kim 001 (ESSCIRC, 2013)

A Process-Variation-Tolerant On-Chip CMOS Thermometer for Auto Temperature Compensated Self-Refresh of Low-Power Mobile DRAM. - Daeyong Shim; Hyunsik Jeong; Hyunjoong Lee; Cyuyeol Rhee; Deog-Kyoon Jeong; Suhwan Kim 001 (IEEE J. Solid State Circuits, 2013)

A 10-Mbps 0.8-pJ/bit Referenceless Clock and Data Recovery Circuit for Optically Controlled Neural Interface System. - Sunkwon Kim; Jong-Kwan Woo; Woo-Yeol Shin; Gi-Moon Hong; Hyongmin Lee; Hyunjoong Lee; Suhwan Kim 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2013)

Bitline Techniques With Dual Dynamic Nodes for Low-Power Register Files. - Rahul Singh; Gi-Moon Hong; Suhwan Kim 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

1.2 V 10-bit 75 MS/s Pipelined ADC With Phase-Dependent Gain-Transition CDS. - Jong-Kwan Woo; Hyunjoong Lee; Hwi-Cheol Kim; Deog-Kyoon Jeong; Suhwan Kim 001 (IEEE Trans. Very Large Scale Integr. Syst., 2014)

A 1.74mW/GHz 0.11-2.5GHz fast-locking, jitter-reducing, 180° phase-shift digital DLL with a window phase detector for LPDDR4 memory controllers. - Joo-Hyung Chae; Gi-Moon Hong; Jihwan Park; Mino Kim; Hyeongjun Ko; Woo-Yeol Shin; Hankyu Chi; Deog-Kyoon Jeong; Suhwan Kim 001 (A-SSCC, 2015)

A 9-bit, 110-MS/s pipelined-SAR ADC using time-interleaved technique with shared comparator. - Taehoon Kim; Sunkwon Kim; Jong-Kwan Woo; Hyongmin Lee; Suhwan Kim 001 (SoCC, 2015)

Low noise output stage for oversampling audio DAC. - Yujin Park; Han Yang 001; Hyunjong Kim; Jun Soo Cho; Suhwan Kim 001 (SoCC, 2015)

Differentiating ASK Demodulator for Contactless Smart Cards Supporting VHBR. - Hyongmin Lee; Jisung Kim; Dongwoo Ha; Taehoon Kim; Suhwan Kim 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

Phase shift keying demodulator with decision feedback phase-locked loop. - Jae-Whan Lee; Mino Kim; Jihwan Park; Gi-Moon Hong; Suhwan Kim 001 (ISCAS, 2016)

A 386-μW, 15.2-bit Programmable-Gain Embedded Delta-Sigma ADC for Sensor Applications. - Jaehoon Jun; Cyuyeol Rhee; Suhwan Kim 001 (ISLPED, 2016)

A current-mirror technique used for high-order curvature compensated bandgap reference in automotive application. - Dongwoo Ha; Yujin Park; Suhwan Kim 001 (MWSCAS, 2016)

A CMOS analog front-end for driving a high-speed SAR ADC in low-power ultrasound imaging systems. - Taehoon Kim; Han Yang 001; Sangmin Shin; Hyongmin Lee; Suhwan Kim 001 (SoCC, 2016)

Column readout circuit with dual integration CDS for infrared imagers. - Yujin Park; Han Yang 001; Jeahyun Ahn; Suhwan Kim 001 (IEICE Electron. Express, 2016)

A Sub-1.0-V On-Chip CMOS Thermometer With a Folded Temperature Sensor for Low-Power Mobile DRAM. - Hyunjoong Lee; Daeyong Shim; Cyuyeol Rhee; Mino Kim; Suhwan Kim 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

A 12.1mW, 60dB SNR, 8-channel beamforming embedded SAR ADC for ultrasound imaging systems. - Taehoon Kim; Suhwan Kim 001 (A-SSCC, 2017)

A 2.1Gbps 12-channel transmitter with phase emphasis embedded serializer for UHD intra-panel interface. - Jihwan Park; Joo-Hyung Chae; Yong-Un Jeong; Jae-Whan Lee; Suhwan Kim 001 (A-SSCC, 2017)

A load variation tolerant readout interface for high linear MEMS capacitive microphones. - Han Yang 001; Jun Soo Cho; Youngtae Yang; Suhwan Kim 001 (ISCAS, 2017)

Power efficient SAR ADC adaptive to input activity for ECG monitoring applications. - Sungwon Yim; Yujin Park; Han Yang 001; Suhwan Kim 001 (ISCAS, 2017)

A 0.13pJ/bit, referenceless transceiver with clock edge modulation for a wired intra-BAN communication. - Jihwan Park; Gi-Moon Hong; Mino Kim; Joo-Hyung Chae; Suhwan Kim 001 (ISLPED, 2017)

An 8Gb/s adaptive DFE with level calibration using training data pattern for mobile DRAM interface. - Minchang Kim; Jihwan Park; Joo-Hyung Chae; Hyeongjun Ko; Mino Kim; Suhwan Kim 001 (ISOCC, 2017)

A constant bandwidth switched-capacitor programmable-gain amplifier utilizing adaptive miller compensation technique. - Hyunjong Kim; Yujin Park; Han Yang 001; Suhwan Kim 001 (SoCC, 2017)

A low-pass continuous-time delta-sigma interface circuit for wideband MEMS gyroscope readout ASIC. - Youngtae Yang; Jaehoon Jun; Suhwan Kim 001 (SoCC, 2017)

Energy-Efficient Dynamic Comparator with Active Inductor for Receiver of Memory Interfaces. - Jae-Whan Lee; Joo-Hyung Chae; Jihwan Park; Hyunkyu Park 002; Jaekwang Yun; Suhwan Kim 001 (ISLPED, 2018)

A 21.8b sub-100μHz 1/f corner 2.4μV-offset programmable-gain read-out IC for bridge measurement systems. - Jaehoon Jun; Cyuyeol Rhee; Minsung Kim; Junho Kang; Suhwan Kim 001 (ISSCC, 2018)

A 3.2 Gb/s 16-Channel Transmitter for Intra-Panel Interfaces, With Independently Controllable Output Swing, Common-Mode Voltage, and Equalization. - Joo-Hyung Chae; Mino Kim; Gi-Moon Hong; Jihwan Park; Suhwan Kim 001 (IEEE Access, 2018)

A 2.1-Gb/s 12-Channel Transmitter With Phase Emphasis Embedded Serializer for 55-in UHD Intra-Panel Interface. - Jihwan Park; Joo-Hyung Chae; Yong-Un Jeong; Jae-Whan Lee; Suhwan Kim 001 (IEEE J. Solid State Circuits, 2018)

A 1.2-V 108.9-dB A-Weighted DR 101.4-dB SNDR Audio ΣΔ ADC Using a Multi-Rate Noise-Shaping Quantizer. - Jun Soo Cho; Cyuyeol Rhee; Susie Kim; Youngtae Yang; Jaehoon Jun; Suhwan Kim 001; Hyunjoong Lee (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

A 4266 Mb/s/pin LPDDR4 Interface With An Asynchronous Feedback CTLE and An Adaptive 3-Step Eye Detection Algorithm for Memory Controller. - Mino Kim; Joo-Hyung Chae; Sungphil Choi; Gi-Moon Hong; Hyeongjun Ko; Deog-Kyoon Jeong; Suhwan Kim 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

A 2-MHz BW 82-dB DR Continuous-Time Delta-Sigma Modulator With a Capacitor-Based Voltage DAC for ELD Compensation. - Susie Kim; Seung-In Na; Youngtae Yang; Suhwan Kim 001 (IEEE Trans. Very Large Scale Integr. Syst., 2018)

An Uncooled Microbolometer Infrared Imager With a Shutter-Based Successive-Approximation Calibration Loop. - Yujin Park; Junghee Yun; Dongchul Park; Sangwoo Kim; Suhwan Kim 001 (IEEE Trans. Very Large Scale Integr. Syst., 2018)

A 20Gb/s Dual-Mode PAM4/NRZ Single-Ended Transmitter with RLM Compensation. - Changho Hyun; Hyeongjun Ko; Joo-Hyung Chae; Hyunkyu Park 002; Suhwan Kim 001 (ISCAS, 2019)

A 16 Bit Incremental ADC with Swapping DAC for Low Power Sensor Applications. - Jaehoon Jun; Junho Kang; Suhwan Kim 001 (ISCAS, 2019)

A Low-Power and Low-Noise 20: 1 Serializer with Two Calibration Loops in 55-nm CMOS. - Yong-Un Jeong; Joo-Hyung Chae; Sungphil Choi; Jaekwang Yun; Shin-Hyun Jeong; Suhwan Kim 001 (ISLPED, 2019)

A Sound Activity Detector Embedded Low-Power MEMS Microphone Readout Interface for Speech Recognition. - Youngtae Yang; Jun Soo Cho; Byunggyu Lee; Suhwan Kim 001 (ISLPED, 2019)

A 370-fJ/b, 0.0056 mm2/DQ, 4.8-Gb/s DQ Receiver for HBM3 with a Baud-Rate Self-Tracking Loop. - Han-Gon Ko; Soyeong Shin; Chan-Ho Kye; Sang-Yoon Lee 006; Jaekwang Yun; Hae-Kang Jung; Doobock Lee; Suhwan Kim 001; Deog-Kyoon Jeong (VLSI Circuits, 2019)

A 22-bit Read-Out IC With 7-ppm INL and Sub-100-µHz 1/ f Corner for DC Measurement Systems. - Jaehoon Jun; Soungchul Park; Junho Kang; Suhwan Kim 001 (IEEE J. Solid State Circuits, 2019)

A 12.8-Gb/s Quarter-Rate Transmitter Using a 4: 1 Overlapped Multiplexing Driver Combined With an Adaptive Clock Phase Aligner. - Joo-Hyung Chae; Hyeongjun Ko; Jihwan Park; Suhwan Kim 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

An 80.2 dB DR 23.25 mW/Channel 8-Channel Ultrasound Receiver With a Beamforming Embedded SAR ADC. - Taehoon Kim; Sangmin Shin; Suhwan Kim 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

A Quadrature Clock Corrector for DRAM Interfaces, With a Duty-Cycle and Quadrature Phase Detector Based on a Relaxation Oscillator. - Joo-Hyung Chae; Hyeongjun Ko; Jihwan Park; Suhwan Kim 001 (IEEE Trans. Very Large Scale Integr. Syst., 2019)

A 0.4-1.7GHz Wide Range Fractional-N PLL Using a Transition-Detection DAC for Jitter Reduction. - Jaekwang Yun; Sangyoon Lee 006; Yong-Un Jeong; Shin-Hyun Jeong; Suhwan Kim 001 (A-SSCC, 2020)

A Sub-1 ppm/°C CMOS Bandgap Voltage Reference With Process Tolerant Piecewise Second-Order Curvature Compensation. - Yongjoon Ahn; Suhwan Kim 001; Hyunjoong Lee (SoCC, 2020)

A 28-Gb/s/pin PAM-4 Single-Ended Transmitter with High-Linearity and Impedance-Matched Driver and 3-Point ZQ Calibration for Memory Interfaces. - Yong-Un Jeong; Hyunkyu Park 002; Changho Hyun; Suhwan Kim 001 (VLSI Circuits, 2020)

A 0.3 lx-1.4 Mlx Monolithic Silicon Nanowire Light-to-Digital Converter With Temperature-Independent Offset Cancellation. - Cyuyeol Rhee; Junyoung Park; Suhwan Kim 001 (IEEE J. Solid State Circuits, 2020)

Data-Dependent Selection of Amplitude and Phase Equalization in a Quarter-Rate Transmitter for Memory Interfaces. - Joo-Hyung Chae; Yong-Un Jeong; Suhwan Kim 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2020)

A 10.4-Gb/s 1-Tap Decision Feedback Equalizer With Different Pull-Up and Pull-Down Tap Weights for Asymmetric Memory Interfaces. - Joo-Hyung Chae; Minchang Kim; Sungphil Choi; Suhwan Kim 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

A 9Gb/s Wide Output Range Transmitter With 2D Binary-Segmented Driver and Dual-Loop Calibration for Intra-Panel Interfaces. - Yong-Un Jeong; Jihwan Park; Mino Kim; Joo-Hyung Chae; Jaekwang Yun; Hyunjoong Lee; Suhwan Kim 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

A Wide Dynamic Range Multi-Mode Band-Pass Continuous-Time Delta-Sigma Modulator Employing Single-Opamp Resonator With Positive Resistor-Feedback. - Susie Kim; Cyuyeol Rhee; Suhwan Kim 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

A 0.83-pJ/Bit 6.4-Gb/s HBM Base Die Receiver Using a 45° Strobe Phase for Energy-Efficient Skew Compensation. - Sangyoon Lee 006; Han-Gon Ko; Joo-Hyung Chae; Soyeong Shin; Jaekwang Yun; Deog-Kyoon Jeong; Suhwan Kim 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

A 0.45 pJ/b, 6.4 Gb/s Forwarded-Clock Receiver With DLL-Based Self-Tracking Loop for Unmatched Memory Interfaces. - Soyeong Shin; Han-Gon Ko; Chan-Ho Kye; Sang-Yoon Lee 006; Jaekwang Yun; Doobock Lee; Hae-Kang Jung; Suhwan Kim 001; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

A Digital Capacitive MEMS Microphone for Speech Recognition With Fast Wake-Up Feature Using a Sound Activity Detector. - Youngtae Yang; Byunggyu Lee; Jun Soo Cho; Suhwan Kim 001; Hyunjoong Lee (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

A Power-Efficient and Fast-Locking Digital Quadrature Clock Generator with Ping-Pong Phase Detection. - Heon Hwa Cheong; Suhwan Kim 001 (ISCAS, 2021)

A High-Accuracy and Fast-Correction Quadrature Signal Corrector Using an Adaptive Delay Gain Controller for Memory Interfaces. - Hyunkyu Park 002; Jihwan Park; Jae-Whan Lee; Yong-Un Jeong; Shin-Hyun Jeong; Suhwan Kim 001; Joo-Hyung Chae (ISCAS, 2021)

Energy-Efficient Read-Out IC for High-Precision DC Measurement System with Instrumentation Amplifier Power Reduction Technique. - Sangmin Shin; Minsung Kim; Junyoung Park; Hyunjoong Lee; Suhwan Kim 001 (ISCAS, 2021)

A Fast-Locking All-Digital PLL With Triple-Stage Phase-Shifting. - Heon Hwa Cheong; Suhwan Kim 001 (IEEE Access, 2021)

A Differentiating Receiver With a Transition-Detecting DFE for Dual-Rank Mobile Memory Interface. - Sungphil Choi; Yong-Un Jeong; Joo-Hyung Chae; Shin-Hyun Jeong; Suhwan Kim 001 (IEEE Access, 2021)

A 0.64-pJ/Bit 28-Gb/s/Pin High-Linearity Single-Ended PAM-4 Transmitter With an Impedance-Matched Driver and Three-Point ZQ Calibration for Memory Interface. - Yong-Un Jeong; Hyunkyu Park 002; Changho Hyun; Joo-Hyung Chae; Shin-Hyun Jeong; Suhwan Kim 001 (IEEE J. Solid State Circuits, 2021)

A Controller PHY for Managed DRAM Solution With Damping-Resistor-Aided Pulse-Based Feed-Forward Equalizer. - Hyeongjun Ko; Mino Kim; Hyunkyu Park 002; Sangyoon Lee 006; Jaewook Kim; Suhwan Kim 001; Joo-Hyung Chae (IEEE J. Solid State Circuits, 2021)

A 19-bit Range and 4.5-ps Resolution Fully-Synthesizable Time-to-Digital Converter with Quad-Edge Offset Cancellation. - Heon Hwa Cheong; Suhwan Kim 001 (ISCAS, 2022)

A 78.8fJ/b/mm 12.0Gb/s/Wire Capacitively Driven On-Chip Link Over 5.6mm with an FFE-Combined Ground-Forcing Biasing Technique for DRAM Global Bus Line in 65nm CMOS. - Sangyoon Lee 006; Jaekwang Yun; Suhwan Kim 001 (ISSCC, 2022)

A Low-Power Digital Capacitive MEMS Microphone Based on a Triple-Sampling Delta-Sigma ADC With Embedded Gain. - Byunggyu Lee; Jinho Yang; Jun Soo Cho; Suhwan Kim 001 (IEEE Access, 2022)

A 24-Gb/s/pin Single-Ended PAM-4 Receiver With 1-Tap Decision Feedback Equalizer Using Inverter-Based Summer for Memory Interfaces. - Hyunkyu Park 002; Yong-Un Jeong; Suhwan Kim 001 (IEEE Access, 2022)

A 10 Gb/s/pin Single-Ended Transmitter With Reflection-Aided Duobinary Modulation for Dual-Rank Mobile Memory Interfaces. - Yong-Un Jeong; Sungphil Choi; Joo-Hyung Chae; Jaekwang Yun; Shin-Hyun Jeong; Suhwan Kim 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A Low-Power DRAM Transmitter With Phase and Current-Mode Amplitude Equalization to Improve Impedance Matching. - Sangyoon Lee 006; Yong-Un Jeong; Jaekwang Yun; Joo-Hyung Chae; Suhwan Kim 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A 56-to-110 dB Gain Programmable Gain Amplifier with Second-Order Band Pass Filter for Ultrasonic Sensor Systems. - Junho Kang; Soungchul Park; Suhwan Kim 001; Jooyeol Rhee (ICEIC, 2023)

A 133.3 dB Dynamic Range Pulse Oximeter Front-End with Low-Noise Area-Efficient Offset Cancellation Current DAC. - Soungchul Park; Wooyoung Kim; Suhwan Kim 001; Jooyeol Rhee (ICEIC, 2023)

A 50-1600 MHz Wide-Range Digital Duty-Cycle Corrector With Counter-Based Half-Cycle Delay Line. - Jaewook Kim; Jaekwang Yun; Joo-Hyung Chae; Suhwan Kim 001 (IEEE Access, 2023)

A 0.85-pJ/b 16-Gb/s/Pin Single-Ended Transmitter With Integrated Voltage Modulation for Low-Power Memory Interfaces. - Yong-Un Jeong; Joo-Hyung Chae; Suhwan Kim 001 (IEEE J. Solid State Circuits, 2023)

Single-Ended Receiver-Side Crosstalk Cancellation With Independent Gain and Timing Control for Minimum Residual FEXT. - Yong-Un Jeong; Sungphil Choi; Suhwan Kim 001; Joo-Hyung Chae (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

A 0.77-pJ/bit 40-Gb/s/pin Single-Ended Hybrid DAC-Based Transmitter for Memory Interfaces. - Sanghyuk Seo; Yong-Un Jeong; Jaekwang Yun; Jaewook Kim; Suhwan Kim 001 (ISCAS, 2024)

A 8Gb/s PAM-4/NRZ Dual-Mode Transmitter for Panel Interfaces with Run-length Limited Maximum Transition. - Goeun Kim; Younghwan Chang; Yong-Un Jeong; Suhwan Kim 001 (SOCC, 2024)

A Single-Ended Impedance-Matched Transmitter With Single Ring-Oscillator-Based Time-Domain ZQ Calibration for Memory Interfaces. - Jaekwang Yun; Sangyoon Lee 006; Jaewook Kim; Joo-Hyung Chae; Suhwan Kim 001; Yong-Un Jeong (IEEE J. Solid State Circuits, 2024)

An N/PBTI-Isolated BTI Monitor With a Configurable Switching Network and Calibration for Process Variation in Memory Periphery. - Shin-Hyun Jeong; Yong-Un Jeong; Suhwan Kim 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

An Energy and Area-Efficient PAM-4 Data Coding Scheme with Embedded Supply Noise Stabilization for Single-Ended Memory Interface. - Giyeong Heo; Younghwan Chang; Yong-Un Jeong; Jaekwang Yun; Jusung Lee; Shin-Hyun Jeong; Sanghyuk Seo; Suhwan Kim 001 (CICC, 2025)

Comprehensive Analysis of Design and Performance Evaluation Methodologies for a High-Resolution Read-Out IC With Ultralow 1/ f Corner for DC Measurement Applications. - Junho Kang; Woosol Han; Suhwan Kim 001; Jaehoon Jun (IEEE Trans. Instrum. Meas., 2025)

Corrections to "Comprehensive Analysis of Design and Performance Evaluation Methodologies for a High-Resolution Read-Out IC With Ultralow 1/ f Corner for DC Measurement Applications". - Junho Kang; Woosol Han; Suhwan Kim 001; Jaehoon Jun (IEEE Trans. Instrum. Meas., 2025)

A 13.2-kSPS Data Rate, 5.1-G Ω Input Impedance Read-Out IC for DC Measurements. - Junyoung Park; Wooyoung Kim; Donghoon Han; Hyunjoong Lee; Suhwan Kim 001; Jooyeol Rhee (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)