Adaptive Learning Rule for Hardware-based Deep Neural Networks Using Electronic Synapse Devices. - Suhwan Lim; Jong-Ho Bae; Jai-Ho Eum; Sungtae Lee; Chul-Heung Kim; Byung-Gook Park; Jong-Ho Lee 002 (CoRR, 2017)

Hardware-based Neural Networks using a Gated Schottky Diode as a Synapse Device. - Suhwan Lim; Jong-Ho Bae; Jai-Ho Eum; Sungtae Lee; Chul-Heung Kim; Dongseok Kwon; Jong-Ho Lee 002 (ISCAS, 2018)

Review of candidate devices for neuromorphic applications. - Jong-Ho Lee 002; Yoohyun Noh; Hyeongsu Kim; Jangsaeng Kim; Jong-Ho Bae; Sung Yun Woo; Sungtae Lee; Suhwan Lim; Won-Mook Kang; Young-Tak Seo; Soochang Lee; Dongseok Kwon; et al. (ESSDERC, 2019)

Investigation of Neural Networks Using Synapse Arrays Based on Gated Schottky Diodes. - Suhwan Lim; Dongseok Kwon; Sungtae Lee; Hyeongsu Kim; Jong-Ho Bae; Jong-Ho Lee 002 (IJCNN, 2019)

Adaptive learning rule for hardware-based deep neural networks using electronic synapse devices. - Suhwan Lim; Jong-Ho Bae; Jai-Ho Eum; Sungtae Lee; Chul-Heung Kim; Dongseok Kwon; Byung-Gook Park; Jong-Ho Lee 002 (Neural Comput. Appl., 2019)

Efficient precise weight tuning protocol considering variation of the synaptic devices and target accuracy. - Hyeongsu Kim; Jong-Ho Bae; Suhwan Lim; Sungtae Lee; Young-Tak Seo; Dongseok Kwon; Byung-Gook Park; Jong-Ho Lee 002 (Neurocomputing, 2020)

Coexistence study on 5G V2X in mmWave. - Jin Woong Park; Jin-Yup Hwang; Suhwan Lim; Yoonoh Yang; Sang-Wook Lee (ICTC, 2021)

Improvement of GIDL-assisted Erase by using Surrounded BL PAD Structure for VNAND. - Suhwan Lim; Samki Kim; Changhee Lee; Hyeongwon Choi; Nambin Kim; Jaehun Jung; Hanvit Yang; Tae-Hun Kim; Junhee Lim; Daewon Ha; Sunghoi Hur; Jae-hoon Jang; et al. (IMW, 2023)

Novel Strategies for Highly Uniform and Reliable Cell Characteristics of 8th Generation 1Tb 3D-NAND Flash Memory. - Changhwan Lee; Min-Tai Yu; Sejun Park; Hoki Lee; Bio Kim; Suhwan Lim; Jaeduk Lee; Sung-Hun Lee; Mincheol Park; Sujin Ahn; Sunghoi Hur (VLSI Technology and Circuits, 2023)

Design Framework for Ferroelectric Gate Stack Engineering of Vertical NAND Structures for Efficient TLC and QLC Operation. - Dipjyoti Das; Lance Fernandes; Prasanna Venkatesan Ravindran; Taeyoung Song; Chinsung Park; Nashrah Afroze; Mengkun Tian; Hang Chen; Winston Chem; Kijoon Kim; Jongho Woo; Suhwan Lim; et al. (IMW, 2024)

Drain Current Degradation Induced by Charge Trapping/De-Trapping in Fe-FET. - Taeyoung Kim; Suhwan Lim; Ilho Myeong; Sanghyun Park; Suseong Noh; Seung Min Lee; Jongho Woo; Hanseung Ko; Youngji Noh; Moonkang Choi; Kiheun Lee; Sangwoo Han; et al. (IRPS, 2024)

A Comprehensive Study of Read-After-Write-Delay for Ferroelectric VNAND. - Ilho Myeong; Suhwan Lim; Taeyoung Kim; Sanghyun Park; Suseong Noh; Seung Min Lee; Jongho Woo; Hanseung Ko; Youngji Noh; Munkang Choi; Kiheun Lee; Sangwoo Han; et al. (IRPS, 2024)

Low-Damage Processed and High-Pressure Annealed High-k Hafnium Zirconium Oxide Capacitors near Morphotropic Phase Boundary with Record-Low EOT of 2.4Å & high-k of 70 for DRAM Technology. - Venkateswarlu Gaddam; Junghyeon Hwang; Hunbeom Shin; Chaeheon Kim; Giuk Kim; Hyung-Jun Kim; Jooho Lee; Hyun-Cheol Kim; Bumsu Park; Suhwan Lim; Sang Yun Kim; Kwangsoo Kim; et al. (VLSI Technology and Circuits, 2024)

In-depth Analysis of the Hafnia Ferroelectrics as a Key Enabler for Low Voltage & QLC 3D VNAND Beyond 1K Layers: Experimental Demonstration and Modeling. - Giuk Kim; Hyojun Choi; Hunbeom Shin; Sangho Lee; Sangmok Lee; Yunseok Nam; Minhyun Jung; Ilho Myeong; Kijoon Kim; Jongho Woo; Suhwan Lim; Kwangsoo Kim; et al. (VLSI Technology and Circuits, 2024)

Paving the Way for Pass Disturb Free Vertical NAND Storage via A Dedicated and String-Compatible Pass Gate. - Zijian Zhao 001; Sola Woo; Khandker Akif Aabrar; Sharadindu Gopal Kirtania; Zhouhang Jiang; Shan Deng; Yi Xiao 008; Halid Mulaosmanovic; Stefan Dünkel; Dominik Kleimaier; Steven Soss; Sven Beyer; et al. (CoRR, 2024)

The Opportunity of Anti-ferroelectrics in FeFET for Emerging Non-Volatile Memory Applications. - Hyojun Choi; Giuk Kim; Hunbeom Shin; Yunseok Nam; Sanghun Jeon; Kwangsoo Kim; Suhwan Lim; Jongho Woo; Wanki Kim; Daewon Ha; Jinho Ahn (IRPS, 2025)

Investigating Read-After-Write Delay in Ferroelectric FET with Gate-Side Injection. - Sizhe Ma; Saikat Chakraborty; Yixin Qin; Zijian Zhao 001; Jiahui Duan; Moonyoung Jung; Kijoon Kim; Suhwan Lim; Kwangyou Seo; Kwangsoo Kim; Wanki Kim; Daewon Ha; et al. (IRPS, 2025)

Retention Analysis of Ferroelectric FETs with Gate-Side Injection for Vertical NAND Storage. - Yixin Qin; Saikat Chakraborty; Zijian Zhao 001; Sizhe Ma; Moonyoung Jung; Kijoon Kim; Suhwan Lim; Kwangyou Seo; Kwangsoo Kim; Wanki Kim; Daewon Ha; Vijaykrishnan Narayanan; et al. (IRPS, 2025)

Enhanced Memory Performance in Ferroelectric NAND Applications: The Role of Tunnel Dielectric Position for Robust 10-Year Retention. - Prasanna Venkatesan Ravindran; Andrea Padovani; Lance Fernandes; Priyankka Gundlapudi Ravikumar; Chinsung Park; Huy Tran; Zekai Wang; Hari Jayasankar; Amrit Garlapati; Taeyoung Song; Hang Chen; Winston Chern; et al. (IRPS, 2025)

Modeling Dynamic Interplay Between Charge Traps and Polarization for Memory Window Enhancement in Gate Injection Layers. - Minji Shon; Chinsung Park; Prasanna Venkatesan Ravindran; Lance Fernandes; Kijoon Kim; Jongho Woo; Suhwan Lim; Kwangsoo Kim; Wanki Kim; Daewon Ha; Suman Datta; Asif Khan; et al. (IRPS, 2025)