Clock Generation and Distribution of a Dual-Core Xeon Processor with 16MB L3 Cache. - Simon Tam 001; Justin Leung; Rahul Dilip Limaye; Sam Choy; Sujal Vora; Mitsuhiro Adachi (ISSCC, 2006)

A 65-nm Dual-Core Multithreaded Xeon® Processor With 16-MB L3 Cache. - Stefan Rusu; Simon M. Tam; Harry Muljono; David Ayers; Jonathan Chang; Brian S. Cherkauer; Jason Stinson; John Benoit; Raj Varada; Justin Leung; Rahul Dilip Limaye; Sujal Vora (IEEE J. Solid State Circuits, 2007)

Power reduction techniques for an 8-core xeon® processor. - Stefan Rusu; Simon M. Tam; Harry Muljono; Jason Stinson; David Ayers; Jonathan Chang; Raj Varada; Matt Ratta; Sailesh Kottapalli; Sujal Vora (ESSCIRC, 2009)

A 45 nm 8-Core Enterprise Xeon¯ Processor. - Stefan Rusu; Simon M. Tam; Harry Muljono; Jason Stinson; David Ayers; Jonathan Chang; Raj Varada; Matt Ratta; Sailesh Kottapalli; Sujal Vora (IEEE J. Solid State Circuits, 2010)

Innovative practices session 10C: Delay test. - P. Pant; M. Amodeo; Sujal Vora; Jonathon E. Colburn (VTS, 2013)

5.4 Ivytown: A 22nm 15-core enterprise Xeon® processor family. - Stefan Rusu; Harry Muljono; David Ayers; Simon M. Tam; Wei Chen 129; Aaron Martin; Shenggao Li; Sujal Vora; Raj Varada; Eddie Wang (ISSCC, 2014)

A 22 nm 15-Core Enterprise Xeon® Processor Family. - Stefan Rusu; Harry Muljono; David Ayers; Simon M. Tam; Wei Chen 129; Aaron Martin; Shenggao Li; Sujal Vora; Raj Varada; Eddie Wang (IEEE J. Solid State Circuits, 2015)

SkyLake-SP: A 14nm 28-Core xeon® processor. - Simon M. Tam; Harry Muljono; Min Huang; Sitaraman Iyer; Kalapi Royneogi; Nagmohan Satti; Rizwan Qureshi; Wei Chen 129; Tom Wang; Hubert Hsieh; Sujal Vora; Eddie Wang (ISSCC, 2018)

Cascade Lake: Next Generation Intel Xeon Scalable Processor. - Mohamed Arafa; Bahaa Fahim; Sailesh Kottapalli; Akhilesh Kumar; Lily Pao Looi; Sreenivas Mandava; Andy Rudoff; Ian M. Steiner; Bob Valentine; Geetha Vedaraman; Sujal Vora (IEEE Micro, 2019)