A Comparative Study of Pseudo Stuck-At and Leakage Fault Model. - Sujit T. Zachariah; Sreejit Chakravarty (VLSI Design, 1999)

A novel algorithm to extract two-node bridges. - Sujit T. Zachariah; Sreejit Chakravarty; Carl D. Roth (DAC, 2000)

A scalable and efficient methodology to extract two node bridges from large industrial circuits. - Sujit T. Zachariah; Sreejit Chakravarty (ITC, 2000)

STBM: a fast algorithm to simulate IDDQ tests forleakage faults. - Sreejit Chakravarty; Sujit T. Zachariah (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000)

A Novel Algorithm for Multi-Node Bridge Analysis of Large VLSI Circuits. - Sujit T. Zachariah; Sreejit Chakravarty (VLSI Design, 2001)

Test Challenges in Nanometer Technologies. - Sandip Kundu; Sujit T. Zachariah; Sanjay Sengupta; Rajesh Galivanche (J. Electron. Test., 2001)

Experimental Evaluation of Scan Tests for Bridges. - Sreejit Chakravarty; Ankur Jain; Nandakumar Radhakrishnan; Eric W. Savage; Sujit T. Zachariah (ITC, 2002)

Layout Analysis to Extract Open Nets Caused by Systematic Failure Mechanisms. - Sreejit Chakravarty; Kambiz Komeyli; Eric W. Savage; Michael J. Carruthers; Bret T. Stastny; Sujit T. Zachariah (VTS, 2002)

On Modeling Cross-Talk Faults. - Sujit T. Zachariah; Yi-Shing Chang; Sandip Kundu; Chandra Tirumurti (DATE, 2003)

Algorithm to extract two-node bridges. - Sujit T. Zachariah; Sreejit Chakravarty (IEEE Trans. Very Large Scale Integr. Syst., 2003)

Physical Design Trends and Layout-Based Fault Modeling. - Susmita Sur-Kolay; Parthasarathi Dasgupta; Bhargab B. Bhattacharya; Sujit T. Zachariah (VLSI Design, 2004)

Extraction of two-node bridges from large industrial circuits. - Sujit T. Zachariah; Sreejit Chakravarty (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

Logic proximity bridges. - Eric N. Tran; Vamsee Krishna; Sujit T. Zachariah; Sreejit Chakravarty (ITC, 2005)

On modeling crosstalk faults. - Sandip Kundu; Sujit T. Zachariah; Yi-Shing Chang; Chandra Tirumurti (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

Test Pattern Generation for Power Supply Droop Faults. - Debasis Mitra 002; Subhasis Bhattacharjee; Susmita Sur-Kolay; Bhargab B. Bhattacharya; Sujit T. Zachariah; Sandip Kundu (VLSI Design, 2006)