15.4 A 280µW 24kHz-BW 98.5dB-SNDR chopped single-bit CT ΔΣM achieving <10Hz 1/f noise corner without chopping artifacts. - Sujith Billa; Amrith Sukumaran; Shanthi Pavan (ISSCC, 2016)

Analysis and Design of Continuous-Time Delta-Sigma Converters Incorporating Chopping. - Sujith Billa; Amrith Sukumaran; Shanthi Pavan (IEEE J. Solid State Circuits, 2017)

A 265μW Continuous-Time 1-2 MASH ADC Achieving 100.6 dB SNDR in a 24 kHz Bandwidth. - Sujith Billa; Suhas Dixit; Shanthi Pavan (A-SSCC, 2019)

A 24mW Chopped CTDSM Achieving 103.5dB SNDR and 107.5dB DR in a 250kHz Bandwidth. - Raviteja Theertham; Prasanth Koottala; Sujith Billa; Shanthi Pavan (VLSI Circuits, 2019)

Analysis and Design of an Audio Continuous-Time 1-X FIR-MASH Delta-Sigma Modulator. - Sujith Billa; Suhas Dixit; Shanthi Pavan (IEEE J. Solid State Circuits, 2020)

Design Techniques for High-Resolution Continuous-Time Delta-Sigma Converters With Low In-Band Noise Spectral Density. - Raviteja Theertham; Prasanth Koottala; Sujith Billa; Shanthi Pavan (IEEE J. Solid State Circuits, 2020)