System-level routing of mixed-signal ASICs in WREN. - Sujoy Mitra; Sudip Nag; Rob A. Rutenbar; L. Richard Carley (ICCAD, 1992)

Testability-oriented channel routing. - Jitendra Khare; Sujoy Mitra; Pranab K. Nag; U. Maly; Rob A. Rutenbar (VLSI Design, 1995)

Substrate-aware mixed-signal macrocell placement in WRIGHT. - Sujoy Mitra; Rob A. Rutenbar; L. Richard Carley; David J. Allstot (IEEE J. Solid State Circuits, 1995)

Generating Layouts for Self-implementing Modules. - James Hwang; Cameron Patterson; S. Mohan; Eric Dellinger; Sujoy Mitra; Ralph Wittig (FPL, 1998)

VHDL Placement Directives for Parametric IP Blocks. - James Hwang; Cameron Patterson; Sujoy Mitra (FCCM, 1999)

Hierarchical Placement Directives for Parametric IP Blocks. - James Hwang; Cameron Patterson; Sujoy Mitra (FPGA, 1999)