Towards a dynamic associativity enabled write prediction based hybrid cache. - Sukarn Agarwal; Hemangee K. Kapoor (VDAT, 2016)

Restricting writes for energy-efficient hybrid cache in multi-core architectures. - Sukarn Agarwal; Hemangee K. Kapoor (VLSI-SoC, 2016)

Targeting inter set write variation to improve the lifetime of non-volatile cache using fellow sets. - Sukarn Agarwal; Hemangee K. Kapoor (VLSI-SoC, 2017)

Lifetime Enhancement of Non-Volatile Caches by Exploiting Dynamic Associativity Management Techniques. - Sukarn Agarwal; Hemangee K. Kapoor (VLSI-SoC (Selected Papers), 2017)

Towards a Better Lifetime for Non-volatile Caches in Chip Multiprocessors. - Sukarn Agarwal; Hemangee K. Kapoor (VLSID, 2017)

Towards Analysing the Effect of Snoozy Caches on the Temperature of Tiled Chip Multi-Processors. - Ashwini A. Kulkarni; Chirag Joshi; Khushboo Rani; Sukarn Agarwal; Shrinivas P. Mahajan; Hemangee K. Kapoor (ISED, 2018)

Non-blocking Gated Buffers for Energy Efficient on-chip Interconnects in the era of Dark Silicon. - Khushboo Rani; Sukarn Agarwal; Hemangee K. Kapoor (ISED, 2018)

Towards Analysing the Effect of Hybrid Caches on the Temperature of Tiled Chip Multi-Processors. - Ashwini A. Kulkarni; Khushboo Rani; Sukarn Agarwal; Shrinivas P. Mahajan; Hemangee K. Kapoor (iSES, 2018)

Fault Tolerance in Network on Chip Using Bypass Path Establishing Packets. - Sharma Priya; Sukarn Agarwal; Hemangee K. Kapoor (VLSID, 2018)

Reuse-Distance-Aware Write-Intensity Prediction of Dataless Entries for Energy-Efficient Hybrid Caches. - Sukarn Agarwal; Hemangee K. Kapoor (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Enhancing the Lifetime of Non-Volatile Caches by Exploiting Module-Wise Write Restriction. - Sukarn Agarwal; Hemangee K. Kapoor (ACM Great Lakes Symposium on VLSI, 2019)

Towards Optimizing Refresh Energy in embedded-DRAM Caches using Private Blocks. - Sheel Sindhu Manohar; Sukarn Agarwal; Hemangee K. Kapoor (ACM Great Lakes Symposium on VLSI, 2019)

Improving the Lifetime of Non-Volatile Cache by Write Restriction. - Sukarn Agarwal; Hemangee K. Kapoor (IEEE Trans. Computers, 2019)

DidaSel: dirty data based selection of VC for effective utilization of NVM buffers in on-chip interconnects. - Khushboo Rani; Sukarn Agarwal; Hemangee K. Kapoor (ISLPED, 2020)

LiNoVo: Longevity Enhancement of Non-Volatile Last Level Caches in Chip Multiprocessors. - Sukarn Agarwal; Hemangee K. Kapoor (ISVLSI, 2020)

Reuse Distance-based Victim Cache for Effective Utilisation of Hybrid Main Memory System. - Arijit Nath; Sukarn Agarwal; Hemangee K. Kapoor (ACM Trans. Design Autom. Electr. Syst., 2020)

ABACa: Access Based Allocation on Set Wise Multi-Retention in STT-RAM Last Level Cache. - Sukarn Agarwal; Shounak Chakraborty 001 (ASAP, 2021)

DAMUS: Dynamic Allocation based on Write Frequency in MUlti-Retention STT-RAM based Last Level Caches. - Mayank Baranwal; Udbhav Chugh; Shivang Dalal; Sukarn Agarwal; Hemangee K. Kapoor (ISQED, 2021)

Improving the Performance of Hybrid Caches Using Partitioned Victim Caching. - Sukarn Agarwal; Hemangee K. Kapoor (ACM Trans. Embed. Comput. Syst., 2021)

Architecting Selective Refresh based Multi-Retention Cache for Heterogeneous System (ARMOUR). - Sukarn Agarwal; Shounak Chakraborty 001; Magnus Själander (DAC, 2023)

Compound Memory Models. - Andrés Goens; Soham Chakraborty 001; Susmit Sarkar; Sukarn Agarwal; Nicolai Oswald; Vijay Nagarajan (Proc. ACM Program. Lang., 2023)

DELICIOUS: Deadline-Aware Approximate Computing in Cache-Conscious Multicore. - Sangeet Saha; Shounak Chakraborty 001; Sukarn Agarwal; Rahul Gangopadhyay; Magnus Själander; Klaus D. McDonald-Maier (IEEE Trans. Parallel Distributed Syst., 2023)

TEEMO: Temperature Aware Energy Efficient Multi-Retention STT-RAM Cache Architecture. - Sukarn Agarwal; Shounak Chakraborty 001; Magnus Själander (IPDPS, 2024)

ARCTIC: Approximate Real-Time Computing in a Cache-Conscious Multicore Environment. - Sangeet Saha; Shounak Chakraborty 001; Sukarn Agarwal; Magnus Själander; Klaus D. McDonald-Maier (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

HotReRAM: A Performance-Power-Thermal Simulation Framework for ReRAM-Based Caches. - Shounak Chakraborty 001; Thanasin Bunnam; Jedsada Arunruerk; Sukarn Agarwal; Shengqi Yu; Rishad A. Shafik; Magnus Själander (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)