23.6 A 0.6V 4.266Gb/s/pin LPDDR4X interface with auto-DQS cleaning and write-VWM training for memory controller. - Soo-Min Lee; Jihun Oh; Jinho Choi; Seokkyun Ko; Daero Kim; Kyounghoi Koo; JongRyun Choi; Yoonjee Nam; Sangsoo Park; Hyungkweon Lee; Eunsu Kim; Sukhyun Jung; et al. (ISSCC, 2017)

22.5 An 8nm 18Gb/s/pin GDDR6 PHY with TX Bandwidth Extension and RX Training Technique. - Soo-Min Lee; Kihwan Seong; Joohee Shin; Hyoungjoong Kim; Jaehyun Jeong; Shinyoung Yi 002; Juyoung Kim; Eunsu Kim; Sukhyun Jung; Sangyun Hwang; Jihun Oh; Kwanyeob Chae; et al. (ISSCC, 2020)

A 4nm 1.15TB/s HBM3 Interface with Resistor-Tuned Offset-Calibration and In-Situ Margin-Detection. - Kwanyeob Chae; Jiyeon Park; Jaegeun Song; Billy Koo; Jihun Oh; Shinyoung Yi 002; Won Lee; Dongha Kim; Taekyung Yeo; Kyeongkeun Kang; Sangsoo Park; Eunsu Kim; et al. (ISSCC, 2023)

A 4nm 32Gb/s 8Tb/s/mm Die-to-Die Chiplet Using NRZ Single-Ended Transceiver With Equalization Schemes And Training Techniques. - Kihwan Seong; Donguk Park; Gyeom-Je Bae; Hyunwoo Lee; Youngseob Suh; Wooseuk Oh; Hyemun Lee; Juyoung Kim; Takgun Lee; Geonhoo Mo; Sukhyun Jung; Dongcheol Choi; et al. (ISSCC, 2023)

Communication and Radar Signal Separation in Overlapping Frequency Bands Using Conv-TasNet. - Sukhyun Jung; Zhiyuan Nan; Haewoon Nam (ICTC, 2024)