Enhancements in Deterministic BIST Implementations for Improving Test of Complex SOCs. - Sandeep Jain; Jais Abraham; Srinivas Kumar Vooka; Sumant Kale; Amit Dutta; Rubin A. Parekhji (VLSI Design, 2007)

Towards effective and compression-friendly test of memory interface logic. - V. R. Devanathan; Alan Hales; Sumant Kale; Dharmesh Sonkar (ITC, 2010)

A reconfigurable built-in memory self-repair architecture for heterogeneous cores with embedded BIST datapath. - V. R. Devanathan; Sumant Kale (ITC, 2016)