FASE: An Open Run-Time Reconfigurable FPGA Architecture for Tamper-Resistant and Secure Embedded Systems. - Sumanta Chaudhuri; Jean-Luc Danger; Sylvain Guilley; Philippe Hoogvorst (ReConFig, 2006)

Efficient Modeling and Floorplanning of Embedded-FPGA Fabric. - Sumanta Chaudhuri; Jean-Luc Danger; Sylvain Guilley (FPL, 2007)

A Novel Asynchronous e-FPGA Architecture for Security Applications. - Taha Beyrouthy; Alin Razafindraibe; Laurent Fesquet; Marc Renaudin; Sumanta Chaudhuri; Sylvain Guilley; Jean-Luc Danger; Philippe Hoogvorst (FPT, 2007)

A Reconfigurable Cell for a Multi-Style Asynchronous FPGA. - Philippe Hoogvorst; Sylvain Guilley; Sumanta Chaudhuri; Alin Razafindraibe; Taha Beyrouthy; Laurent Fesquet (ReCoSoC, 2007)

Physical Design of FPGA Interconnect to Prevent Information Leakage. - Sumanta Chaudhuri; Sylvain Guilley; Philippe Hoogvorst; Jean-Luc Danger; Taha Beyrouthy; Alin Razafindraibe; Laurent Fesquet; Marc Renaudin (ARC, 2008)

An 8x8 run-time reconfigurable FPGA embedded in a SoC. - Sumanta Chaudhuri; Sylvain Guilley; Florent Flament; Philippe Hoogvorst; Jean-Luc Danger (DAC, 2008)

Efficient tiling patterns for reconfigurable gate arrays. - Sumanta Chaudhuri; Jean-Luc Danger; Philippe Hoogvorst; Sylvain Guilley (FPGA, 2008)

Place-and-Route Impact on the Security of DPL Designs in FPGAs. - Sylvain Guilley; Sumanta Chaudhuri; Jean-Luc Danger; Laurent Sauvage; Philippe Hoogvorst; Maxime Nassar; Tarik Graba; Vinh-Nga Vong (HOST, 2008)

A Reconfigurable Programmable Logic Block for a Multi-Style Asynchronous FPGA resistant to Side-Channel Attacks - Philippe Hoogvorst; Sylvain Guilley; Sumanta Chaudhuri; Jean-Luc Danger; Taha Beyrouthy; Laurent Fesquet (CoRR, 2008)

Security Evaluation of WDDL and SecLib Countermeasures against Power Attacks. - Sylvain Guilley; Laurent Sauvage; Philippe Hoogvorst; Renaud Pacalet; Guido Marco Bertoni; Sumanta Chaudhuri (IEEE Trans. Computers, 2008)

Diagonal tracks in FPGAs: a performance evaluation. - Sumanta Chaudhuri (FPGA, 2009)

Updates on the potential of clock-less logics to strengthen cryptographic circuits against side-channel attacks. - Sylvain Guilley; Sumanta Chaudhuri; Laurent Sauvage; Jean-Luc Danger; Taha Beyrouthy; Laurent Fesquet (ICECS, 2009)

High Density Asynchronous LUT Based on Non-volatile MRAM Technology. - Sumanta Chaudhuri; Weisheng Zhao; Jacques-Olivier Klein; Claude Chappert; Pascale Mazoyer (FPL, 2010)

Design of embedded MRAM macros for memory-in-logic applications. - Sumanta Chaudhuri; Weisheng Zhao; Jacques-Olivier Klein; Claude Chappert; Pascale Mazoyer (ACM Great Lakes Symposium on VLSI, 2010)

Timing speculation in FPGAs: Probabilistic inference of data dependent failure rates. - Sumanta Chaudhuri; Justin S. J. Wong; Peter Y. K. Cheung (FPT, 2011)

A Secure Asynchronous FPGA Architecture, Experimental Results and Some Debug Feedback - Sumanta Chaudhuri; Sylvain Guilley; Philippe Hoogvorst; Jean-Luc Danger; Taha Beyrouthy; Alin Razafindraibe; Laurent Fesquet; Marc Renaudin (CoRR, 2011)

Side-Channel Oscilloscope - Sumanta Chaudhuri; Sylvain Guilley (CoRR, 2011)

A two-stage variation-aware placement method for FPGAS exploiting variation maps classification. - Zhenyu Guan; Justin S. J. Wong; Sumanta Chaudhuri; George A. Constantinides; Peter Y. K. Cheung (FPL, 2012)

Cross-point architecture for spin transfer torque magnetic random access memory - Weisheng Zhao; Sumanta Chaudhuri; Celso Accoto; Jacques-Olivier Klein; Claude Chappert; Pascale Mazoyer (CoRR, 2012)

A variation-adaptive retiming method exploiting reconfigurability. - Zhenyu Guan; Justin S. J. Wong; Sumanta Chaudhuri; George A. Constantinides; Peter Y. K. Cheung (FPL, 2013)

Exploiting stochastic delay variability on FPGAs with adaptive partial rerouting. - Zhenyu Guan; Justin S. J. Wong; Sumanta Chaudhuri; George A. Constantinides; Peter Y. K. Cheung (FPT, 2013)

Classification on variation maps: a new placement strategy to alleviate process variation on FPGA. - Zhenyu Guan; Justin S. J. Wong; Sumanta Chaudhuri; George A. Constantinides; Peter Y. K. Cheung (IEICE Electron. Express, 2014)

Mitigation of process variation effect in FPGAs with partial rerouting method. - Zhenyu Guan; Justin S. J. Wong; Sumanta Chaudhuri; George A. Constantinides; Peter Y. K. Cheung (IEICE Electron. Express, 2014)

Multi-Valued Routing Tracks for FPGAs in 28nm FDSOI Technology. - Sumanta Chaudhuri; Tarik Graba; Yves Mathieu (CoRR, 2016)

Cache Timing Attacks from The SoCFPGA Coherency Port (Abstract Only). - Sumanta Chaudhuri (FPGA, 2017)

A security vulnerability analysis of SoCFPGA architectures. - Sumanta Chaudhuri (DAC, 2018)

Beyond Bits: A Quaternary FPGA Architecture Using Multi-Vt Multi-Vdd FDSOI Devices. - Sumanta Chaudhuri (ISMVL, 2018)

Quad-Approx CNNs for Embedded Object Detection Systems. - Xuecan Yang; Sumanta Chaudhuri; Lirida A. B. Naviner; Laurence Likforman (ICECS, 2020)

Minconvnets: a New Class of Multiplication-Less Neural Networks. - Xuecan Yang; Sumanta Chaudhuri; Laurence Likforman; Lirida A. B. Naviner (ICIP, 2022)

A Hitchhiker's Guide to White-Box Neural Network Watermarking Robustness. - Carl De Sousa Trias; Mihai Mitrea; Enzo Tartaglione; Attilio Fiandrotti; Marco Cagnazzo; Sumanta Chaudhuri (EUVIP, 2023)

A gem5 based Platform for Micro-Architectural Security Analysis. - Quentin Forcioli; Jean-Luc Danger; Sumanta Chaudhuri (HASP@MICRO, 2023)

Find the Lady: Permutation and Re-synchronization of Deep Neural Networks. - Carl De Sousa Trias; Mihai Petru Mitrea; Attilio Fiandrotti; Marco Cagnazzo; Sumanta Chaudhuri; Enzo Tartaglione (AAAI, 2024)

WaterMAS: Sharpness-Aware Maximization for Neural Network Watermarking. - Carl De Sousa Trias; Mihai Mitrea; Attilio Fiandrotti; Marco Cagnazzo; Sumanta Chaudhuri; Enzo Tartaglione (ICPR (5), 2024)

TEE-Time: A Dynamic Cache Timing Analysis Tool for Trusted Execution Environments. - Quentin Forcioli; Sumanta Chaudhuri; Jean-Luc Danger (ISQED, 2024)

Defeating AutoLock: From Simulation to Real-World Cache-Timing Exploits against TrustZone. - Quentin Forcioli; Sumanta Chaudhuri; Jean-Luc Danger (IACR Cryptol. ePrint Arch., 2025)

Lightweight Embedded FPGA Deployment of Learned Image Compression with Knowledge Distillation and Hybrid Quantization. - Alaa Mazouz; Sumanta Chaudhuri; Marco Cagnazzo; Mihai Mitrea; Enzo Tartaglione; Attilio Fiandrotti (CoRR, 2025)

Security and Real-time FPGA integration for Learned Image Compression. - Alaa Mazouz; Carl De Sousa Trias; Sumanta Chaudhuri; Attilio Fiandrotti; Marco Cagnazzo; Mihai Mitrea; Enzo Tartaglione (CoRR, 2025)