Energy-Efficient VLSI Architecture & Implementation of Bi-modal Multi-banked Register-File Organization. - Sumanth Gudaparthi; Rahul Shrestha (VDAT, 2017)

Moving CNN Accelerator Computations Closer to Data. - Sumanth Gudaparthi; Surya Narayanan; Rajeev Balasubramonian (EMC2@ASPLOS, 2018)

Wire-Aware Architecture and Dataflow for CNN Accelerators. - Sumanth Gudaparthi; Surya Narayanan; Rajeev Balasubramonian; Edouard Giacomin; Hari Kambalasubramanyam; Pierre-Emmanuel Gaillardon (MICRO, 2019)

CANDLES: Channel-Aware Novel Dataflow-Microarchitecture Co-Design for Low Energy Sparse Neural Network Acceleration. - Sumanth Gudaparthi; Sarabjeet Singh; Surya Narayanan; Rajeev Balasubramonian; Visvesh Sathe 001 (HPCA, 2022)

Selective register-file cache: an energy saving technique for embedded processor architecture. - Sumanth Gudaparthi; Rahul Shrestha (Des. Autom. Embed. Syst., 2022)

PATHFINDER: Practical Real-Time Learning for Data Prefetching. - Lin Jia; James Patrick Mcmahon; Sumanth Gudaparthi; Shreyas Singh; Rajeev Balasubramonian (ASPLOS (3), 2024)

Hyena: Balancing Packing, Reuse, and Rotations for Encrypted Inference. - Sarabjeet Singh; Shreyas Singh; Sumanth Gudaparthi; Xiong Fan; Rajeev Balasubramonian (SP, 2024)