Learning Based Timing Closure on Relative Timed Design. - Tannu Sharma; Sumanth Kolluru; Kenneth S. Stevens (VLSI-SoC (Selected Papers), 2020)

Behavioral Simulation of Relative Timed Asynchronous Circuits. - Sumanth Kolluru; Kenneth S. Stevens (VLSI-SoC, 2024)

Timing Closure in Relative Timed Asynchronous Designs using Deep Reinforcement Learning. - Sumanth Kolluru; Kenneth S. Stevens (ASYNC, 2025)