A technique to determine power-efficient, high-performance superscalar processors. - Thomas M. Conte; Kishore N. Menezes; Sumedh W. Sathaye (HICSS (1), 1995)

Dynamic rescheduling: a technique for object code compatibility in VLIW architectures. - Thomas M. Conte; Sumedh W. Sathaye (MICRO, 1995)

Instruction Fetch Mechanisms for VLIW Architectures with Compressed Encodings. - Thomas M. Conte; Sanjeev Banerjia; Sergei Y. Larin; Kishore N. Menezes; Sumedh W. Sathaye (MICRO, 1996)

A Persistent Rescheduled-page Cache for Low Overhead Object Code Compatibility in VLIW Architectures. - Thomas M. Conte; Sumedh W. Sathaye; Sanjeev Banerjia (MICRO, 1996)

Path Prediction for High Issue-Rate Processors. - Kishore N. Menezes; Sumedh W. Sathaye; Thomas M. Conte (IEEE PACT, 1997)

Optimization of VLIW compatibility systems employing dynamic rescheduling. - Thomas M. Conte; Sumedh W. Sathaye (Int. J. Parallel Program., 1997)

A Fast Interrupt Handling Scheme for VLIW Processors. - Emre Özer 001; Sumedh W. Sathaye; Kishore N. Menezes; Sanjeev Banerjia; Matthew D. Jennings; Thomas M. Conte (IEEE PACT, 1998)

MPS: Miss-Path Scheduling for Multiple-Issue Processors. - Sanjeev Banerjia; Sumedh W. Sathaye; Kishore N. Menezes; Thomas M. Conte (IEEE Trans. Computers, 1998)

Execution-Based Scheduling for VLIW Architectures. - Kemal Ebcioglu; Erik R. Altman; Sumedh W. Sathaye; Michael Gschwind (Euro-Par, 1999)

Optimizations and Oracle Parallelism with Dynamic Translation. - Kemal Ebcioglu; Erik R. Altman; Sumedh W. Sathaye; Michael Gschwind (MICRO, 1999)

Binary translation and architecture convergence issues for IBM system/390. - Michael Gschwind; Kemal Ebcioglu; Erik R. Altman; Sumedh W. Sathaye (ICS, 2000)

Dynamic and Transparent Binary Translation. - Michael Gschwind; Erik R. Altman; Sumedh W. Sathaye; Paul Ledak; David Appenzeller (Computer, 2000)

Properties of Rescheduling Size Invariance for Dynamic Rescheduling-Based VLIW Cross-Generation Compatibility. - Thomas M. Conte; Sumedh W. Sathaye (IEEE Trans. Computers, 2000)

System-level power consumption modeling and tradeoff analysis techniques for superscalar processor design. - Thomas M. Conte; Kishore N. Menezes; Sumedh W. Sathaye; Mark C. Toburen (IEEE Trans. Very Large Scale Integr. Syst., 2000)

Dynamic Binary Translation and Optimization. - Kemal Ebcioglu; Erik R. Altman; Michael Gschwind; Sumedh W. Sathaye (IEEE Trans. Computers, 2001)

Preface. - Erik R. Altman; Sumedh W. Sathaye (IBM J. Res. Dev., 2006)