Automatic Correctness Proof of the Implementation of Synchronous Sequential Circuits Using an Algebraic Approach. - Junji Kitamichi; Sumio Morioka; Teruo Higashino; Kenichi Taniguchi (TPCD, 1994)

Fault-Tolerant Refresh Power Reduction of DRAMs for Quasi-Nonvolatile Data Retention. - Yasunao Katayama; Eric J. Stuckey; Sumio Morioka; Zhao Wu (DFT, 1999)

Design Methodology for a One-Shot Reed-Solomon Encoder and Decoder. - Sumio Morioka; Yasunao Katayama (ICCD, 1999)

Efficient Error Correction Code Configurations for Quasi-Nonvolatile Data Retention by DRAMs. - Yasunao Katayama; Yasushi Negishi; Sumio Morioka (DFT, 2000)

One-Shot Reed-Solomon Decoding for High-Performance Dependable Systems. - Yasunao Katayama; Sumio Morioka (DSN, 2000)

A Compact Rijndael Hardware Architecture with S-Box Optimization. - Akashi Satoh; Sumio Morioka; Kohji Takano; Seiji Munetoh (ASIACRYPT, 2001)

Towards Efficient Verification of Arithmetic Algorithms over Galois Fields GF(2m). - Sumio Morioka; Yasunao Katayama; Toshiyuki Yamane (CAV, 2001)

An Optimized S-Box Circuit Architecture for Low Power AES Design. - Sumio Morioka; Akashi Satoh (CHES, 2002)

Small and High-Speed Hardware Architectures for the 3GPP Standard Cipher KASUMI. - Akashi Satoh; Sumio Morioka (ISC, 2002)

Unified Hardware Architecture for 128-Bit Block Ciphers AES and Camellia. - Akashi Satoh; Sumio Morioka (CHES, 2003)

Hardware-Focused Performance Comparison for the Standard Block Ciphers AES, Camellia, and Triple-DES. - Akashi Satoh; Sumio Morioka (ISC, 2003)

A 10-Gbps full-AES crypto design with a twisted BDD S-Box architecture. - Sumio Morioka; Akashi Satoh (IEEE Trans. Very Large Scale Integr. Syst., 2004)

Flexible architecture optimization and ASIC implementation of group signature algorithm using a customized HLS methodology. - Sumio Morioka; Toshiyuki Isshiki; Satoshi Obana; Yuichi Nakamura 002; Kazue Sako (HOST, 2011)

$ textnormal{ textsc{TWINE}}$ : A Lightweight Block Cipher for Multiple Platforms. - Tomoyasu Suzaki; Kazuhiko Minematsu; Sumio Morioka; Eita Kobayashi (Selected Areas in Cryptography, 2012)

A hierarchical formal approach to verifying side-channel resistant cryptographic processors. - Kotaro Okamoto; Naofumi Homma; Takafumi Aoki; Sumio Morioka (HOST, 2014)

CLOC: Authenticated Encryption for Short Input. - Tetsu Iwata; Kazuhiko Minematsu; Jian Guo 001; Sumio Morioka (IACR Cryptol. ePrint Arch., 2014)

A High Throughput/Gate AES Hardware Architecture by Compressing Encryption and Decryption Datapaths - Toward Efficient CBC-Mode Implementation. - Rei Ueno; Sumio Morioka; Naofumi Homma; Takafumi Aoki (IACR Cryptol. ePrint Arch., 2016)

Automatic generation of formally-proven tamper-resistant Galois-field multipliers based on generalized masking scheme. - Rei Ueno; Naofumi Homma; Sumio Morioka; Takafumi Aoki (DATE, 2017)

Hierarchical Formal Verification Combining Algebraic Transformation with PPRM Expansion and Its Application to Masked Cryptographic Processors. - Rei Ueno; Naofumi Homma; Takafumi Aoki; Sumio Morioka (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)

Tweakable TWINE: Building a Tweakable Block Cipher on Generalized Feistel Structure. - Kosei Sakamoto; Kazuhiko Minematsu; Nao Shibata; Maki Shigeri; Hiroyasu Kubo; Yuki Funabiki; Andrey Bogdanov; Sumio Morioka; Takanori Isobe 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2020)

High Throughput/Gate AES Hardware Architectures Based on Datapath Compression. - Rei Ueno; Naofumi Homma; Sumio Morioka; Noriyuki Miura; Kohei Matsuda; Makoto Nagata; Shivam Bhasin; Yves Mathieu; Tarik Graba; Jean-Luc Danger (IEEE Trans. Computers, 2020)

A Systematic Design Methodology of Formally Proven Side-Channel-Resistant Cryptographic Hardware. - Rei Ueno; Naofumi Homma; Sumio Morioka; Takafumi Aoki (IEEE Des. Test, 2021)

On Cryptographic Algorithms and Key Length for Delayed Disclosure Authentication of GNSS. - Maki Yoshida; Sumio Morioka; Satoshi Obana (ICL-GNSS, 2022)

Secure Communication via GNSS-based Key Synchronization. - Maki Yoshida; Sumio Morioka; Satoshi Obana (WIPHAL, 2023)

Feasibility Study with Actual Space Rockets Towards Information Theoretically Secure Radio Communication. - Sumio Morioka; Satoshi Obana; Maki Yoshida (SAI (2), 2024)

Formal Verification of Composite Field Multipliers for Information-Theoretically Secure Radio Communication in Spacecraft Control. - Sumio Morioka; Satoshi Obana; Maki Yoshida (NFM, 2025)