A 16-ns 1-Mb CMOS EPROM. - Masao Kuriyama; Shigeru Atsumi; Ken-ichi Imamiya; Yumiko Iyama; Naohiro Matsukawa; Hitoshi Araki; Kazuhito Narita; Kazunori Masuda; Sumio Tanaka (IEEE J. Solid State Circuits, 1990)

A 62-ns 16-Mb CMOS EPROM with voltage stress relaxation technique. - Naoto Tomita; Nobuaki Ohtsuka; Jun-ichi Miyamoto; Ken-ichi Imamiya; Yumiko Iyama; Seiichi Mori; Yoichi Ohshima; Norihisa Arai; Yukio Kaneko; Eiji Sakagami; Kuniyoshi Yoshikawa; Sumio Tanaka (IEEE J. Solid State Circuits, 1991)

A 5-V-only operation 0.6- mu m flash EEPROM with row decoder scheme in triple-well structure. - Akira Umezawa; Shigeru Atsumi; Masao Kuriyama; Hironori Banba; Ken-ichi Imamiya; Kiyomi Naruke; Seiji Yamada; Etsushi Obi; Masamitsu Oshikiri; Tomoko Suzuki; Sumio Tanaka (IEEE J. Solid State Circuits, 1992)

A 0.5-μm, 3-V 1T1C, 1-Mbit FRAM with a variable reference bit-line voltage scheme using a fatigue-free reference capacitor. - Ryu Ogiwara; Sumio Tanaka; Yasuo Itoh; Tadashi Miyakawa; Yoshiaki Takeuchi; Sumiko Mano Doumae; Hiroyuki Takenaka; Iwao Kunishima; Susumu Shuto; Osamu Hidaka; Sumito Ohtsuki; Shin'ichi Tanaka (IEEE J. Solid State Circuits, 2000)