Complexity of Scheduling in Synthesizing Hardware from Concurrent Action Oriented Specifications. - Gaurav Singh 006; S. S. Ravi; Sumit Ahuja; Sandeep K. Shukla (Power-aware Computing Systems, 2007)

Model-driven test generation for system level validation. - Deepak Mathaikutty; Sumit Ahuja; Ajit Dingankar; Sandeep K. Shukla (HLDVT, 2007)

VT Matrix Multiply Design for MEMOCODE '07. - Eric Simpson; Pengyuan Yu; Patrick Schaumont; Sumit Ahuja; Sandeep K. Shukla (MEMOCODE, 2007)

Assertion-Based Modal Power Estimation. - Sumit Ahuja; Deepak Mathaikutty; Sandeep K. Shukla; Ajit Dingankar (MTV, 2007)

Techniques for Power-Aware Hardware Synthesis from Concurrent Action Oriented Specifications. - Gaurav Singh 006; Jacob B. Schwartz; Sumit Ahuja; Sandeep K. Shukla (J. Low Power Electron., 2007)

Applying Verification Collaterals for Accurate Power Estimation. - Sumit Ahuja; Deepak Mathaikutty; Sandeep K. Shukla (MTV, 2008)

MCBCG: Model Checking Based Sequential Clock-Gating. - Sumit Ahuja; Sandeep K. Shukla (HLDVT, 2009)

Power estimation methodology for a high-level synthesis framework. - Sumit Ahuja; Deepak Mathaikutty; Gaurav Singh 006; Joe Stetzer; Sandeep K. Shukla; Ajit Dingankar (ISQED, 2009)

Accurate power estimation of hardware co-processors using system level simulation. - Sumit Ahuja; Deepak Mathaikutty; Avinash Lakshminarayana; Sandeep K. Shukla (SoCC, 2009)

Hardware Coprocessor Synthesis from an ANSI C Specification. - Sumit Ahuja; Swathi T. Gurumani; Chad Spackman; Sandeep K. Shukla (IEEE Des. Test Comput., 2009)

SCoPE: Statistical Regression Based Power Models for Co-Processors Power Estimation. - Sumit Ahuja; Deepak Mathaikutty; Avinash Lakshminarayana; Sandeep K. Shukla (J. Low Power Electron., 2009)

The Model Checking View to Clock Gating and Operand Isolation. - Jens Brandt 001; Klaus Schneider 001; Sumit Ahuja; Sandeep K. Shukla (ACSD, 2010)

System level simulation guided approach to improve the efficacy of clock-gating. - Sumit Ahuja; Wei Zhang; Sandeep K. Shukla (HLDVT, 2010)

Coprocessor design space exploration using high level synthesis. - Avinash Lakshminarayana; Sumit Ahuja; Sandeep K. Shukla (ISQED, 2010)

A Methodology for Power Aware High-Level Synthesis of Co-processors from Software Algorithms. - Sumit Ahuja; Wei Zhang; Avinash Lakshminarayana; Sandeep K. Shukla (VLSI Design, 2010)

Power Aware High Level Synthesis of Hardware Coprocessors. - Sumit Ahuja; Wei Zhang; Avinash Lakshminarayana; Sandeep K. Shukla (J. Low Power Electron., 2010)

High Level Power Estimation and Reduction Techniques for Power Aware Hardware Design. - Sumit Ahuja (2010)

High Level Power Estimation Models for FPGAs. - Avinash Lakshminarayana; Sumit Ahuja; Sandeep K. Shukla (ISVLSI, 2011)

Low Power Design with High-Level Power Estimation and Power-Aware Synthesis. - Sumit Ahuja; Avinash Lakshminarayana; Sandeep Kumar Shukla (Springer, 2012)