Implementation of a 32-bit RISC Processor for the Data-Intensive Architecture Processing-In-Memory Chip. - Jeffrey T. Draper; Jeff Sondeen; Sumit D. Mediratta; Ihn Kim (ASAP, 2002)

An Area-Efficient Router for the Data-Intensive Architecture (DIVA) System. - Sumit D. Mediratta; Jeff Sondeen; Jeffrey T. Draper (VLSI Design, 2004)

Performance Analysis of User-Level PIM Communication in the Data IntensiVe Architecture (DIVA) System. - Sumit D. Mediratta; Jeffrey T. Draper (HiPC, 2005)

An area-efficient and protected network interface for processing-in-memory systems. - Sumit D. Mediratta; Craig S. Steele; Jeff Sondeen; Jeffrey T. Draper (ISCAS (3), 2005)

A Prototype Processing-In-Memory (PIM) Chip for the Data-Intensive Architecture (DIVA) System. - Jeffrey T. Draper; Tim Barrett; Jeff Sondeen; Sumit D. Mediratta; Chang Woo Kang; Ihn Kim; Gokhan Daglikoca (J. VLSI Signal Process., 2005)

A double-data rate (DDR) processing-in-memory (PIM) device with wideword floating-point capability. - Tim Barrett; Sumit D. Mediratta; Taek-Jun Kwon; Ravinder Singh; Sachit Chandra; Jeff Sondeen; Jeffrey T. Draper (ISCAS, 2006)

Performance Evaluation of Probe-Send Fault-tolerant Network-on-chip Router. - Sumit D. Mediratta; Jeffrey T. Draper (ASAP, 2007)

Characterization of a Fault-tolerant NoC Router. - Sumit D. Mediratta; Jeffrey T. Draper (ISCAS, 2007)