A Sub-0.5V Reliability Aware-Negative Bitline Write-Assisted 8T DP-SRAM and WL Strapping Novel Architecture to Counter Dual Patterning Issues in 10nm FinFET. - Vinay Kumar; Nikhil Puri; Sudhir Kumar 002; Sumit Srivastav (VLSID, 2017)

A 7-Nm Dual Port 8T SRAM with Duplicated Inter-Port Write Data to Mitigate Write Disturbance. - M. Sultan M. Siddiqui; Sumit Srivastav; Dattatray Ramrao Wanjul; Manankumar Suthar; Sudhir Kumar 002 (VLSID, 2018)