A 0.5-μm, 3-V 1T1C, 1-Mbit FRAM with a variable reference bit-line voltage scheme using a fatigue-free reference capacitor. - Ryu Ogiwara; Sumio Tanaka; Yasuo Itoh; Tadashi Miyakawa; Yoshiaki Takeuchi; Sumiko Mano Doumae; Hiroyuki Takenaka; Iwao Kunishima; Susumu Shuto; Osamu Hidaka; Sumito Ohtsuki; Shin'ichi Tanaka (IEEE J. Solid State Circuits, 2000)

A 64Mb Chain FeRAM with Quad-BL Architecture and 200MB/s Burst Mode. - Katsuhiko Hoya; Daisaburo Takashima; Shinichiro Shiratake; Ryu Ogiwara; Tadashi Miyakawa; Hidehiro Shiga; Sumiko M. Doumae; Sumito Ohtsuki; Yoshinori Kumura; Susumu Shuto; Tohru Ozaki; Koji Yamakawa; et al. (ISSCC, 2006)

A 64-Mb Chain FeRAM With Quad BL Architecture and 200 MB/s Burst Mode. - Katsuhiko Hoya; Daisaburo Takashima; Shinichiro Shiratake; Ryu Ogiwara; Tadashi Miyakawa; Hidehiro Shiga; Sumiko M. Doumae; Sumito Ohtsuki; Yoshinori Kumura; Susumu Shuto; Tohru Ozaki; Koji Yamakawa; et al. (IEEE Trans. Very Large Scale Integr. Syst., 2010)