A 7b 1GS/s 7.2mW nonbinary 2b/cycle SAR ADC with register-to-DAC direct control. - Hyeok-Ki Hong; Wan Kim; Sun-Jae Park; Michael Choi; Ho-Jin Park; Seung-Tak Ryu (CICC, 2012)

A Decision-Error-Tolerant 45 nm CMOS 7b 1 GS/s Nonbinary 2b/Cycle SAR ADC. - Hyeok-Ki Hong; Wan Kim; Hyun-Wook Kang; Sun-Jae Park; Michael Choi; Ho-Jin Park; Seung-Tak Ryu (IEEE J. Solid State Circuits, 2015)

A 12-bit 10GS/s 16-Channel Time-Interleaved ADC with a Digital Processing Timing-Skew Background Calibration in 5nm FinFET. - Kyoung-Jun Moon; Dong-Ryeol Oh; Young-Hyo Park; Kyung-Hoon Lee; Sun-Jae Park; Sung-No Lee; Hee-Chang Hwang; Hyo-Chul Shin; Young-Jae Cho; Michael Choi; Jongshin Shin (VLSI Technology and Circuits, 2022)

A 12-bit 10GS/s Time-Interleaved SAR ADC with Even/Odd Channel-Correlated Absolute Error-Based Over-Nyquist Timing-Skew Calibration in 5nm FinFET. - Junsang Park; Jinwoo Park; Jaemin Hong; Sun-Jae Park; Dongsuk Lee; Sungno Lee; Hyochul Shin; Kyung-Hoon Lee; Byeongwoo Koo; Youngjae Cho; Michael Choi; Jongshin Shin (VLSI Technology and Circuits, 2024)