Control Circuit Templates for Asynchronous Bundled-Data Pipelines. - Sunan Tugsinavisut; Peter A. Beerel (DATE, 2002)

Reducing probabilistic timed petri nets for asynchronous architectural analysis. - Sangyun Kim 001; Sunan Tugsinavisut; Peter A. Beerel (Timing Issues in the Specification and Synthesis of Digital Systems, 2002)

An asynchronous pipeline comparisons with application to DCT matrix-vector multiplication. - Sunan Tugsinavisut; Suwicha Jirayucharoensak; Peter A. Beerel (ISCAS (5), 2003)

Efficient asynchronous bundled-data pipelines for DCT matrix-vector multiplication. - Sunan Tugsinavisut; Youpyo Hong; Daewook Kim; Kyeounsoo Kim; Peter A. Beerel (IEEE Trans. Very Large Scale Integr. Syst., 2005)

High-level Synthesis for Highly Concurrent Hardware Systems. - Sunan Tugsinavisut; Roger Su; Peter A. Beerel (ACSD, 2006)