PONO: Power Optimization with Near Optimal SMT-based Sub-circuit Generation. - Sunan Zou; Guojie Luo (DAC, 2024)

BESWAC: Boosting Exact Synthesis via Wiser SAT Solver Call. - Sunan Zou; Jiaxi Zhang 001; Bizhao Shi; Guojie Luo (DATE, 2024)

ImageMap: Enabling Efficient Mapping from Image Processing DSL to CGRA. - Bizhao Shi; Tuo Dai; Sunan Zou; Xinming Wei; Guojie Luo (Euro-Par (1), 2024)

Incremental SAT-based Exact Synthesis. - Sunan Zou; Jiaxi Zhang 001; Guojie Luo (ACM Great Lakes Symposium on VLSI, 2024)

AceRoute: Adaptive Compute-Efficient FPGA Routing with Pluggable Intra-Connection Bidirectional Exploration. - Xinming Wei; Ziyun Zhang; Sunan Zou; Kaiwen Sun; Jiahao Zhang; Jiaxi Zhang 001; Ping Fan; Guojie Luo (ICCAD, 2024)

MuSA: Multi-Sketch Accelerator with Hybrid Parallelism and Coalesced Memory Organization. - Sunan Zou; Bizhao Shi; Ziyun Zhang; Guojie Luo (ICCD, 2024)

Large circuit models: opportunities and challenges. - Lei Chen; Yiqi Chen; Zhufei Chu; Wenji Fang; Tsung-Yi Ho; Ru Huang 001; Yu Huang 005; Sadaf Khan; Min Li; Xingquan Li; Yu Li; Yun Liang 001; et al. (Sci. China Inf. Sci., 2024)

Erratum to: Large circuit models: opportunities and challenges. - Lei Chen; Yiqi Chen; Zhufei Chu; Wenji Fang; Tsung-Yi Ho; Ru Huang 001; Yu Huang 005; Sadaf Khan; Min Li; Xingquan Li; Yu Li; Yun Liang 001; et al. (Sci. China Inf. Sci., 2024)

The Dawn of AI-Native EDA: Promises and Challenges of Large Circuit Models. - Lei Chen 002; Yiqi Chen; Zhufei Chu; Wenji Fang; Tsung-Yi Ho; Yu Huang 005; Sadaf Khan; Min Li 019; Xingquan Li; Yun Liang 001; Yibo Lin; Jinwei Liu; et al. (CoRR, 2024)

PowerSyn: A Logic Synthesis Framework With Early Power Optimization. - Sunan Zou; Jiaxi Zhang 001; Bizhao Shi; Guojie Luo (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

UltraSketchLLM: Saliency-Driven Sketching for Ultra-Low Bit LLM Compression. - Sunan Zou; Ziyun Zhang; Xueting Sun; Guojie Luo (CoRR, 2025)