Design and implementation of an ordered memory access architecture. - Sundararajan Sriram; Edward A. Lee (ICASSP (1), 1993)

Minimizing Synchronization Overhead in Statically Scheduled Multiprocessor Systems. - Shuvra S. Bhattacharyya; Sundararajan Sriram; Edward A. Lee (ASAP, 1995)

Latency-constrained Resynchronization for Multiprocessor DSP Implementation. - Shuvra S. Bhattacharyya; Sundararajan Sriram; Edward A. Lee (ASAP, 1996)

Self-Timed Resynchronization: A Post-Optimization for Static Multiprocessor Schedules. - Shuvra S. Bhattacharyya; Sundararajan Sriram; Edward A. Lee (IPPS, 1996)

Performance analysis and optimization of mixed asynchronous synchronous systems. - Jürgen Teich; Lothar Thiele; Sundararajan Sriram; Michael Martin 002 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

Optimizing synchronization in multiprocessor DSP systems. - Shuvra S. Bhattacharyya; Sundararajan Sriram; Edward A. Lee (IEEE Trans. Signal Process., 1997)

Determining the Order of Processor Transactions in Statically Scheduled Multiprocessors. - Sundararajan Sriram; Edward A. Lee (J. VLSI Signal Process., 1997)

Top-Down Design Using Cycle Based Simulation: an MPEG A/V Decoder Example. - Dale E. Hocevar; Ching-Yu Hung; Dan Pickens; Sundararajan Sriram (Great Lakes Symposium on VLSI, 1998)

Fast acquisition method for DS-CDMA systems employing asynchronous base stations. - Sundararajan Sriram; Srinath Hosur (ICC, 1999)

Cyclically permutable codes for rapid acquisition in DS-CDMA systems with asynchronous base stations. - Sundararajan Sriram; Srinath Hosur (IEEE J. Sel. Areas Commun., 2001)