A 2.5-V, 72-Mbit, 2.0-GByte/s packet-based DRAM with a 1.0-Gbps/pin interface. - Changhyun Kim; Kye-Hyun Kyung; W.-P. Jeong; J.-S. Kim; Byung-Sik Moon; Joon-Wan Chai; S.-M. Yim; Jung-Hwan Choi; K.-H. Han; C.-J. Park; Hong-Sun Hwang; H. Choi; et al. (IEEE J. Solid State Circuits, 1999)

A 2.5-V 2.0-Gbyte/s 288-Mb packet-based DRAM with enhanced cell efficiency and noise immunity. - Kyehyun Kyung; Hi-Choon Lee; Ki-Whan Song; Ho-Sung Song; Keewook Jung; Joon-Seo Moon; Byoung-Sul Kim; Sung-Burn Cho; Changhyun Kim; Soo-In Cho (IEEE J. Solid State Circuits, 2001)