Local NOR and global NAND match-line architecture for high performance CAM. - Sung-Gi Ahn; Kee-Won Kwon (MWSCAS, 2017)

Low Power Search Engine using Non-volatile Memory based TCAM with Priority Encoding and Selective Activation of Search Line and Match Line. - Cheol Kim; Rak-Joo Sung; Sung-Gi Ahn; Jisu Min; Kee-Won Kwon (ISCAS, 2018)

Power Efficient and Reliable Nonvolatile TCAM With Hi-PFO and Semi-Complementary Driver. - Cheol Kim; Sung-Gi Ahn; Jisu Min; Kee-Won Kwon (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

A 16-GB 640-GB/s HBM2E DRAM With a Data-Bus Window Extension Technique and a Synergetic On-Die ECC Scheme. - Ki Chul Chun; Yong-Ki Kim; Yesin Ryu; Jaewon Park; Chi Sung Oh; Young-Yong Byun; So-Young Kim; Dong-Hak Shin; Jun Gyu Lee 002; Byung-Kyu Ho; Min-Sang Park; Seong-Jin Cho; et al. (IEEE J. Solid State Circuits, 2021)

A 16 GB 1024 GB/s HBM3 DRAM with On-Die Error Control Scheme for Enhanced RAS Features. - Yesin Ryu; Young-Cheon Kwon; Jaehoon Lee 005; Sung-Gi Ahn; Jaewon Park; Kijun Lee; Yu Ho Choi; Han-Won Cho; Jae San Kim; Jungyu Lee 002; Haesuk Lee; Seung Ho Song; et al. (VLSI Technology and Circuits, 2022)

A 16 GB 1024 GB/s HBM3 DRAM With Source-Synchronized Bus Design and On-Die Error Control Scheme for Enhanced RAS Features. - Yesin Ryu; Sung-Gi Ahn; Jaehoon Lee 005; Jaewon Park; Yong-Ki Kim; Hyochang Kim; Yeong Geol Song; Han-Won Cho; Sunghye Cho; Seung Ho Song; Haesuk Lee; Useung Shin; et al. (IEEE J. Solid State Circuits, 2023)