Concatenated BCH codes for NAND flash memories. - Sung-Gun Cho; Jeongseok Ha (ICC, 2012)

Block-Wise Concatenated BCH Codes for NAND Flash Memories. - Sung-Gun Cho; Daesung Kim; Jinho Choi 001; Jeongseok Ha (IEEE Trans. Commun., 2014)

Error patterns in belief propagation decoding of polar codes and their mitigation methods. - Shuanghong Sun; Sung-Gun Cho; Zhengya Zhang (ACSSC, 2016)

A 2.56mm2 718GOPS configurable spiking convolutional sparse coding processor in 40nm CMOS. - Chester Liu; Sung-Gun Cho; Zhengya Zhang (A-SSCC, 2017)

Post-Processing Methods for Improving Coding Gain in Belief Propagation Decoding of Polar Codes. - Shuanghong Sun; Sung-Gun Cho; Zhengya Zhang (GLOBECOM, 2017)

A 2.56-mm2 718GOPS Configurable Spiking Convolutional Sparse Coding Accelerator in 40-nm CMOS. - Chester Liu; Sung-Gun Cho; Zhengya Zhang (IEEE J. Solid State Circuits, 2018)

A 2048-Neuron Spiking Neural Network Accelerator With Neuro-Inspired Pruning And Asynchronous Network On Chip In 40nm CMOS. - Sung-Gun Cho; Edith Beigné; Zhengya Zhang (CICC, 2019)

A 3.25Gb/s, 13.2pJ/b, 0.64mm2 Configurable Successive-Cancellation List Polar Decoder using Split-Tree Architecture in 40nm CMOS. - Yaoyu Tao; Sung-Gun Cho; Zhengya Zhang (VLSI Circuits, 2019)

PETRA: A 22nm 6.97TFLOPS/W AIB-Enabled Configurable Matrix and Convolution Accelerator Integrated with an Intel Stratix 10 FPGA. - Sung-Gun Cho; Wei Tang 010; Chester Liu; Zhengya Zhang (VLSI Circuits, 2021)

A Configurable Successive-Cancellation List Polar Decoder Using Split-Tree Architecture. - Yaoyu Tao; Sung-Gun Cho; Zhengya Zhang (IEEE J. Solid State Circuits, 2021)

Arvon: A Heterogeneous SiP Integrating a 14nm FPGA and Two 22nm 1.8TFLOPS/W DSPs with 1.7Tbps/mm2 AIB 2.0 Interface to Provide Versatile Workload Acceleration. - Wei Tang 010; Sung-Gun Cho; Tim Tri Hoang; Jacob Botimer; Wei Qiang Zhu; Ching-Chi Chang; Cheng-Hsun Lu; Junkang Zhu; Yaoyu Tao; Tianyu Wei; Naomi Kavi Motwani; Mani Yalamanchi; et al. (VLSI Technology and Circuits, 2023)

Arvon: A Heterogeneous System-in-Package Integrating FPGA and DSP Chiplets for Versatile Workload Acceleration. - Wei Tang 010; Sung-Gun Cho; Tim Tri Hoang; Jacob Botimer; Wei Qiang Zhu; Ching-Chi Chang; Cheng-Hsun Lu; Junkang Zhu; Yaoyu Tao; Tianyu Wei; Naomi Kavi Motwani; Mani Yalamanchi; et al. (IEEE J. Solid State Circuits, 2024)