An accurate timing model for fault simulation in MOS circuits. - Sungho Kim 006; Prithviraj Banerjee (ICCAD, 1989)

A Layout Driven Design for Testability Technique for MOS VLSI Circuits. - Sungho Kim 006; Prithviraj Banerjee; Srinivas Patil (ITC, 1991)

APT: An Area-Performance-Testability Driven Placement Algorithm. - Sungho Kim 006; Prithviraj Banerjee; Vivek Chickermane; Janak H. Patel (DAC, 1992)

Improved Algorithms for Cell Placement and Their Parallel Implementations - Sungho Kim 006 (1993)

ProperPLACE: A Portable Parallel Algorithm for Standard Cell Placement. - Sungho Kim 006; Prithviraj Banerjee; Balkrishna Ramkumar; Steven Parkes; John A. Chandy (IPPS, 1994)

An evaluation of parallel simulated annealing strategies with application to standard cell placement. - John A. Chandy; Sungho Kim 006; Balkrishna Ramkumar; Steven Parkes; Prithviraj Banerjee (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)