A 101-dB SNR hybrid delta-sigma audio ADC using post integration time control. - Moo-Yeol Choi; Sung-No Lee; Seung-Bin You; Wang-Seup Yeum; Ho-Jin Park; Jae-Whui Kim; Hae-Seung Lee (CICC, 2008)

An 11mW 100MHz 16X-OSR 64dB-SNDR hybrid CT/DT ΔΣ ADC with relaxed DEM timing. - Sunwoo Kwon; Pavan Kumar Hanumolu; Sang-Ho Kim; Sung-No Lee; Seung-Bin You; Ho-Jin Park; Jae-Whui Kim; Un-Ku Moon (CICC, 2009)

A 12-bit 10GS/s 16-Channel Time-Interleaved ADC with a Digital Processing Timing-Skew Background Calibration in 5nm FinFET. - Kyoung-Jun Moon; Dong-Ryeol Oh; Young-Hyo Park; Kyung-Hoon Lee; Sun-Jae Park; Sung-No Lee; Hee-Chang Hwang; Hyo-Chul Shin; Young-Jae Cho; Michael Choi; Jongshin Shin (VLSI Technology and Circuits, 2022)