Analysis of Check-Node Merging Decoding for Punctured LDPC Codes with Dual-Diagonal Parity Structure. - Jung-Ae Kim; Sung-Rae Kim; Dong-Joon Shin; Song-Nam Hong 001 (WCNC, 2007)

Lowering Error Floors of Systematic LDPC Codes Using Data Shortening. - Sung-Rae Kim; Dong-Joon Shin (IEEE Commun. Lett., 2013)

A post-processing algorithm for reducing strong error effects in NAND flash memory. - Sung-Rae Kim; Kijun Lee; Gyuyeol Kong; Myung-Kyu Lee; Dongmin Shin; Geunyeong Yu; Beomkyu Shin; Pilsang Yoon; Hongrak Son; Jun Jin Kong (APCCAS, 2016)

A 16 GB 1024 GB/s HBM3 DRAM with On-Die Error Control Scheme for Enhanced RAS Features. - Yesin Ryu; Young-Cheon Kwon; Jaehoon Lee 005; Sung-Gi Ahn; Jaewon Park; Kijun Lee; Yu Ho Choi; Han-Won Cho; Jae San Kim; Jungyu Lee 002; Haesuk Lee; Seung Ho Song; et al. (VLSI Technology and Circuits, 2022)

A 16 GB 1024 GB/s HBM3 DRAM With Source-Synchronized Bus Design and On-Die Error Control Scheme for Enhanced RAS Features. - Yesin Ryu; Sung-Gi Ahn; Jaehoon Lee 005; Jaewon Park; Yong-Ki Kim; Hyochang Kim; Yeong Geol Song; Han-Won Cho; Sunghye Cho; Seung Ho Song; Haesuk Lee; Useung Shin; et al. (IEEE J. Solid State Circuits, 2023)