A 13.8mW 3.0Gb/s clock-embedded video interface with DLL-based data-recovery circuit. - Sungchun Jang; Heesoo Song; Seokmin Ye; Deog-Kyoon Jeong (ISSCC, 2011)

A Four-Channel 32-Gb/s Transceiver With Current-Recycling Output Driver and On-Chip AC Coupling in 65-nm CMOS Process. - Taeho Kim; Sungchun Jang; Sungwoo Kim 001; Sang-Hyeok Chu; Jiheon Park; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

A 20 Gb/s 0.4 pJ/b energy-efficient transmitter driver architecture utilizing constant Gm. - Gyu-Seob Jeong; Sang-Hyeok Chu; Yoonsoo Kim; Sungchun Jang; Sungwoo Kim 001; Woo-Rham Bae; Sung-Yong Cho; Haram Ju; Deog-Kyoon Jeong (A-SSCC, 2015)

A 5-GHz subharmonically injection-locked all-digital PLL with complementary switched injection. - Sung-Yong Cho; Sungwoo Kim 001; Min-Seong Choo; Jinhyung Lee; Han-Gon Ko; Sungchun Jang; Sang-Hyeok Chu; Woo-Rham Bae; Yoonsoo Kim; Deog-Kyoon Jeong (ESSCIRC, 2015)

A compact 22-Gb/s transmitter for optical links with all-digital phase-locked loop. - Sungwoo Kim 001; Sungchun Jang; Jun-Eun Park; Yoonsoo Kim; Gyungock Kim; Deog-Kyoon Jeong (ISCAS, 2015)

An all-digital bang-bang PLL using two-point modulation and background gain calibration for spread spectrum clock generation. - Sungchun Jang; Sungwoo Kim 001; Sang-Hyeok Chu; Gyu-Seob Jeong; Yoonsoo Kim; Deog-Kyoon Jeong (VLSIC, 2015)

A 22 to 26.5 Gb/s Optical Receiver With All-Digital Clock and Data Recovery in a 65 nm CMOS Process. - Sang-Hyeok Chu; Woo-Rham Bae; Gyu-Seob Jeong; Sungchun Jang; Sungwoo Kim 001; Jiho Joo; Gyungock Kim; Deog-Kyoon Jeong (IEEE J. Solid State Circuits, 2015)

An Optimum Loop Gain Tracking All-Digital PLL Using Autocorrelation of Bang-Bang Phase-Frequency Detection. - Sungchun Jang; Sungwoo Kim 001; Sang-Hyeok Chu; Gyu-Seob Jeong; Yoonsoo Kim; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

A 20 Gb/s 0.4 pJ/b Energy-Efficient Transmitter Driver Utilizing Constant- Gm Bias. - Gyu-Seob Jeong; Sang-Hyeok Chu; Yoonsoo Kim; Sungchun Jang; Sungwoo Kim 001; Woo-Rham Bae; Sung-Yong Cho; Haram Ju; Deog-Kyoon Jeong (IEEE J. Solid State Circuits, 2016)

A 55.1 mW 1.62-to-8.1 Gb/s Video Interface Receiver Generating up to 680 MHz Stream Clock Over 20 dB Loss Channel. - Kwanseo Park; Jinhyung Lee; Kwangho Lee; Min-Seong Choo; Sungchun Jang; Sang-Hyeok Chu; Sungwoo Kim 001; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

A 1.1V 1ynm 6.4Gb/s/pin 16Gb DDR5 SDRAM with a Phase-Rotator-Based DLL, High-Speed SerDes and RX/TX Equalization Scheme. - Dongkyun Kim; Minsu Park; Sungchun Jang; Jun-Yong Song; Hankyu Chi; Geunho Choi; Sunmyung Choi; Jaeil Kim; Changhyun Kim; Kyung Whan Kim; Kibong Koo; Seonghwi Song; et al. (ISSCC, 2019)

22.6 A 0.8-to-2.3GHz Quadrature Error Corrector with Correctable Error Range of 101.6ps Using Minimum Total Delay Tracking and Asynchronous Calibration On-Off Scheme for DRAM Interface. - Soyeong Shin; Han-Gon Ko; Sungchun Jang; Dongkyun Kim; Deog-Kyoon Jeong (ISSCC, 2020)

A 1.1-V 10-nm Class 6.4-Gb/s/Pin 16-Gb DDR5 SDRAM With a Phase Rotator-ILO DLL, High-Speed SerDes, and DFE/FFE Equalization Scheme for Rx/Tx. - Dongkyun Kim; Kibong Koo; Yongmi Kim; Dong-Uk Lee; Jaejin Lee; Ki Hun Kwon; Byeongchan Choi; Hongjung Kim; Sanghyun Ku; Jong-Sam Kim; Seungwook Oh; Minsu Park; et al. (IEEE J. Solid State Circuits, 2020)