New design error modeling and metrics for design validation. - Sungho Kang 001; Stephen A. Szygenda (EURO-DAC, 1992)

Modeling and Simulation of Design Errors. - Sungho Kang 001; Stephen A. Szygenda (ICCD, 1992)

Automatic VHDL Model Generation System. - Sungho Kang 001; Stephen A. Szygenda (CHDL, 1993)

Design Validation: Comparing Theoretical and Empirical Results of Design Error Modeling. - Sungho Kang 001; Stephen A. Szygenda (IEEE Des. Test Comput., 1994)

Automatic Simulator Generation System. - Sungho Kang 001; Stephen A. Szygenda (Simul., 1994)

The simulation automation system (SAS); concepts, implementation, and results. - Sungho Kang 001; Stephen A. Szygenda (IEEE Trans. Very Large Scale Integr. Syst., 1994)

Massively Parallel Array Processor for Logic, Fault, and Design Error Simulation. - Youngmin Hur; Stephen A. Szygenda; E. Scott Fehr; Granville E. Ott; Sungho Kang 001 (HPCA, 1995)

A Hardware Accelerator for Fault Simulation Utilizing a Reconfigurable Array Architecture. - Sungho Kang 001; Youngmin Hur; Stephen A. Szygenda (VLSI Design, 1996)

At-Speed Boundary-Scan Interconnect Testing in a Board with Multiple System Clocks. - Jongchul Shin; Hyunjin Kim; Sungho Kang 001 (DATE, 1999)

An Efficient Interconnect Test Using BIST Module in a Boundary-Scan Environment. - Hyunjin Kim; Jongchul Shin; Sungho Kang 001 (ICCD, 1999)

A Heuristic for Multiple Weight Set Generation. - Hong-Sik Kim; Jin-kyue Lee; Sungho Kang 001 (ICCD, 2001)

A new multiple weight set calculation algorithm. - Hong-Sik Kim; Jin-kyue Lee; Sungho Kang 001 (ITC, 2001)

An Efficient On-Line Monitoring BIST for Remote Service System. - Sangmin Bae; DongSup Song; Jihye Kim 002; Sungho Kang 001 (AISA, 2002)

A New DSP Architecture for Correcting Errors Using Viterbi Algorithm. - Sungchul Yoon; Sangwook Kim; Jae Seuk Oh; Sungho Kang 001 (AISA, 2002)

DPSC SRAM Transparent Test Algorithm. - Hong-Sik Kim; Sungho Kang 001 (Asian Test Symposium, 2002)

A New Maximal Diagnosis Algorithm for Bus-structured Systems. - YongJoon Kim; DongSub Song; YongSeung Shin; Sunghoon Chun; Sungho Kang 001 (ITC, 2003)

Accurate Logic Simulation by Overcoming the Unknown Value Propagation Problem. - Sungho Kang 001; Stephen A. Szygenda (Simul., 2003)

Test-decompression mechanism using a variable-length multiple-polynomial LFSR. - Hong-Sik Kim; YongJoon Kim; Sungho Kang 001 (IEEE Trans. Very Large Scale Integr. Syst., 2003)

RAIN (RAndom Insertion) Scheduling Algorithm for SoC Test. - Jung-Been Im; Sunghoon Chun; Geunbae Kim; Jin-Ho Ahn; Sungho Kang 001 (Asian Test Symposium, 2004)

Route Reinforcement for Efficient QoS Routing Based on Ant Algorithm. - Jae Seuk Oh; Sung-il Bae; Jin-Ho Ahn; Sungho Kang 001 (ICOIN, 2004)

An In-Order SMT Architecture with Static Resource Partitioning for Consumer Applications. - Byung In Moon; Hongil Yoon; Ilgu Yun; Sungho Kang 001 (PDCAT, 2004)

An Acceleration Processor for Data Intensive Scientific Computing. - Cheong Ghil Kim; Hong-Sik Kim; Sungho Kang 001; Shin-Dug Kim; Gunhee Han (IEICE Trans. Inf. Syst., 2004)

A new maximal diagnosis algorithm for interconnect test. - YongJoon Kim; Hyun-Don Kim; Sungho Kang 001 (IEEE Trans. Very Large Scale Integr. Syst., 2004)

A Practical Test Scheduling Using Network-Based TAM in Network on Chip Architecture. - Jin-Ho Ahn; Byung In Moon; Sungho Kang 001 (Asia-Pacific Computer Systems Architecture Conference, 2005)

Increasing Embedding Probabilities of RPRPs in RIN Based BIST. - DongSup Song; Sungho Kang 001 (Asia-Pacific Computer Systems Architecture Conference, 2005)

A New Low Power Test Pattern Generator using a Transition Monitoring Window based on BIST Architecture. - Youbean Kim; Myung-Hoon Yang; Yong Lee 002; Sungho Kang 001 (Asian Test Symposium, 2005)

An Effective Built-In Self-Test for Chargepump PLL. - Junseok Han; DongSup Song; Hagbae Kim; Youngyong Kim; Sungho Kang 001 (IEICE Trans. Electron., 2005)

An Effective Test Pattern Generation for Testing Signal Integrity. - YongJoon Kim; Myung-Hoon Yang; Youngkyu Park; Daeyeal Lee; Sungho Kang 001 (ATS, 2006)

SoC Test Scheduling Algorithm Using ACO-Based Rectangle Packing. - Jin-Ho Ahn; Sungho Kang 001 (ICIC (2), 2006)

System on a Chip Implementation of Social Insect Behavior for Adaptive Network Routing. - Jin-Ho Ahn; Hyunjin Kim; Byung In Moon; Sungho Kang 001 (ICIC (2), 2006)

Improved Reinforcement Computing to Implement AntNet-Based Routing Using General NPs for Ubiquitous Environments. - Hyuntae Park; Byung In Moon; Sungho Kang 001 (ICUCT, 2006)

An Efficient Dictionary Organization for Maximum Diagnosis. - Sunghoon Chun; Sangwook Kim; Hong-Sik Kim; Sungho Kang 001 (J. Electron. Test., 2006)

A Clustered RIN BIST Based on Signal Probabilities of Deterministic Test Sets. - DongSup Song; Sungho Kang 001 (IEICE Trans. Inf. Syst., 2006)

Increasing encoding efficiency of LFSR reseeding-based test compression. - Hong-Sik Kim; Sungho Kang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

MICRO: a new hybrid test data compression/decompression scheme. - Sunghoon Chun; YongJoon Kim; Jung-Been Im; Sungho Kang 001 (IEEE Trans. Very Large Scale Integr. Syst., 2006)

High-MDSI: A High-level Signal Integrity Fault Test Pattern Generation Method for Interconnects. - Sunghoon Chun; YongJoon Kim; Sungho Kang 001 (ATS, 2007)

MDSI: Signal Integrity Interconnect Fault Modeling and Testing for SoCs. - Sunghoon Chun; YongJoon Kim; Sungho Kang 001 (J. Electron. Test., 2007)

A New Analog-to-Digital Converter BIST Considering a Transient Zone. - Incheol Kim; Kicheol Kim; Youbean Kim; HyeonUk Son; Sungho Kang 001 (IEICE Trans. Electron., 2007)

Deterministic built-in self-test using split linear feedback shift register reseeding for low-power testing. - Myung-Hoon Yang; Youbean Kim; Youngkyu Park; D. Lee; Sungho Kang 001 (IET Comput. Digit. Tech., 2007)

XPDF-ATPG: An Efficient Test Pattern Generation for Crosstalk-Induced Faults. - Sunghoon Chun; YongJoon Kim; Taejin Kim; Myung-Hoon Yang; Sungho Kang 001 (ATS, 2008)

An Effective Hybrid Test Data Compression Method Using Scan Chain Compaction and Dictionary-Based Scheme. - Taejin Kim; Sunghoon Chun; YongJoon Kim; Myung-Hoon Yang; Sungho Kang 001 (ATS, 2008)

An Efficient Scan Chain Diagnosis Method Using a New Symbolic Simulation. - Sunghoon Chun; Taejin Kim; YongJoon Kim; Sungho Kang 001 (VTS, 2008)

A New Scan Architecture for Both Low Power Testing and Test Volume Compression Under SOC Test Environment. - Hong-Sik Kim; Sungho Kang 001; Michael S. Hsiao (J. Electron. Test., 2008)

An Effective Power Reduction Methodology for Deterministic BIST Using Auxiliary LFSR. - Myung-Hoon Yang; YongJoon Kim; Sunghoon Chun; Sungho Kang 001 (J. Electron. Test., 2008)

Ant colony based efficient triplet calculation methodology for arithmetic built-in self test. - Hong-Sik Kim; Hyunjin Kim; Sungho Kang 001 (IEICE Electron. Express, 2008)

A Low-Cost BIST Based on Histogram Testing for Analog to Digital Converters. - Kicheol Kim; Youbean Kim; Incheol Kim; HyeonUk Son; Sungho Kang 001 (IEICE Trans. Electron., 2008)

MTR-Fill: A Simulated Annealing-Based X-Filling Technique to Reduce Test Power Dissipation for Scan-Based Designs. - DongSup Song; Jin-Ho Ahn; Taejin Kim; Sungho Kang 001 (IEICE Trans. Inf. Syst., 2008)

Total Energy Minimization of Real-Time Tasks in an On-Chip Multiprocessor Using Dynamic Voltage Scaling Efficiency Metric. - Hyunjin Kim; Hyejeong Hong; Hong-Sik Kim; Jin-Ho Ahn; Sungho Kang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

An Ant Colony Optimization Approach for the Preference-Based Shortest Path Search. - Seung Ho Ok; Woo-Jin Seo; Jin-Ho Ahn; Sungho Kang 001; Byung In Moon (FGIT-FGCN, 2009)

An Efficient Hardware Architecture of the A-star Algorithm for the Shortest Path Search Engine. - Woo-Jin Seo; Seung Ho Ok; Jin-Ho Ahn; Sungho Kang 001; Byung In Moon (NCM, 2009)

FPGA-based verification methodology of SoC-type CMOS image signal processor. - Younsun Kim; Hong-Sik Kim; R. Lee; Sungho Kang 001 (SoCC, 2009)

A High-Level Signal Integrity Fault Model and Test Methodology for Long On-Chip Interconnections. - Sunghoon Chun; YongJoon Kim; Taejin Kim; Sungho Kang 001 (VTS, 2009)

A memory-efficient parallel string matching for intrusion detection systems. - Hyunjin Kim; Hyejeong Hong; Hong-Sik Kim; Sungho Kang 001 (IEEE Commun. Lett., 2009)

Selective scan slice repetition for simultaneous reduction of test power consumption and test data volume. - YongJoon Kim; Jaeseok Park; Sungho Kang 001 (IEICE Electron. Express, 2009)

Grouped Scan Slice Repetition Method for Reducing Test Data Volume and Test Application Time. - YongJoon Kim; Myung-Hoon Yang; Jaeseok Park; Eunsei Park; Sungho Kang 001 (IEICE Trans. Inf. Syst., 2009)

An Effective Programmable Memory BIST for Embedded Memory. - Youngkyu Park; Jaeseok Park; Taewoo Han; Sungho Kang 001 (IEICE Trans. Inf. Syst., 2009)

A Pattern Group Partitioning for Parallel String Matching using a Pattern Grouping Metric. - Hyunjin Kim; Sungho Kang 001 (IEEE Commun. Lett., 2010)

A memory-efficient heterogeneous parallel pattern matching scheme in deep packet inspection. - Hyunjin Kim; Hyejeong Hong; Dongmyoung Baek; Jin-Ho Ahn; Sungho Kang 001 (IEICE Electron. Express, 2010)

A high performance network-on-chip scheme using lossless data compression. - Hong-Sik Kim; Young H. Jung; Hyunjin Kim; Jin-Ho Ahn; Woo-Chan Park; Sungho Kang 001 (IEICE Electron. Express, 2010)

A Hardware-Efficient Pattern Matching Architecture Using Process Element Tree for Deep Packet Inspection. - Seongyong Ahn; Hyejeong Hong; Hyunjin Kim; Jin-Ho Ahn; Dongmyong Baek; Sungho Kang 001 (IEICE Trans. Commun., 2010)

A Pattern Partitioning Algorithm for Memory-Efficient Parallel String Matching in Deep Packet Inspection. - Hyunjin Kim; Hyejeong Hong; Dongmyong Baek; Sungho Kang 001 (IEICE Trans. Commun., 2010)

A Memory-Efficient Pattern Matching with Hardware-Based Bit-Split String Matchers for Deep Packet Inspection. - Hyunjin Kim; Hong-Sik Kim; Jung-Hee Lee; Jin-Ho Ahn; Sungho Kang 001 (IEICE Trans. Commun., 2010)

A Selective Scan Chain Activation Technique for Minimizing Average and Peak Power Consumption. - YongJoon Kim; Jaeseok Park; Sungho Kang 001 (IEICE Trans. Inf. Syst., 2010)

Selective Scan Slice Grouping Technique for Efficient Test Data Compression. - YongJoon Kim; Jaeseok Park; Sungho Kang 001 (IEICE Trans. Inf. Syst., 2010)

A Fast IP Address Lookup Algorithm Based on Search Space Reduction. - Hyuntae Park; Hyunjin Kim; Hong-Sik Kim; Sungho Kang 001 (IEICE Trans. Commun., 2010)

EOF: Efficient Built-In Redundancy Analysis Methodology With Optimal Repair Rate. - Myung-Hoon Yang; Hyungjun Cho; Wooheon Kang; Sungho Kang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

An Efficient IP Address Lookup Scheme Using Balanced Binary Search with Minimal Entry and Optimal Prefix Vector. - Hyuntae Park; Hyejeong Hong; Sungho Kang 001 (IEICE Trans. Commun., 2011)

Noise-Tolerant DAC BIST Scheme Using Integral Calculus Approach. - HyeonUk Son; Incheol Kim; Sang-Goog Lee; Jin-Ho Ahn; Jeong-Do Kim; Sungho Kang 001 (IEICE Trans. Electron., 2011)

Communication-aware task scheduling and voltage selection for total energy minimization in a multiprocessor system using Ant Colony Optimization. - Hyunjin Kim; Sungho Kang 001 (Inf. Sci., 2011)

A Lossless Color Image Compression Architecture Using a Parallel Golomb-Rice Hardware CODEC. - Hong-Sik Kim; Joohong Lee; Hyunjin Kim; Sungho Kang 001; Woo-Chan Park (IEEE Trans. Circuits Syst. Video Technol., 2011)

A Memory-Efficient Bit-Split Parallel String Matching Using Pattern Dividing for Intrusion Detection Systems. - Hyunjin Kim; Hong-Sik Kim; Sungho Kang 001 (IEEE Trans. Parallel Distributed Syst., 2011)

Integration of dual channel timing formatter system for high speed memory test equipment. - Jaeseok Park; Ingeol Lee; Young-Seok Park; Sung-Geun Kim; Kyungho Ryu; Dong-Hoon Jung; Kangwook Jo; Choong Keun Lee; Hongil Yoon; Seong-Ook Jung; Woo-Young Choi; Sungho Kang 001 (ISOCC, 2012)

An efficient IP address lookup algorithm based on a small balanced tree using entry reduction. - Hyuntae Park; Hyejeong Hong; Sungho Kang 001 (Comput. Networks, 2012)

A method for the fast diagnosis of multiple defects using an efficient candidate selection algorithm. - Yoseop Lim; Jaeseok Park; Sungho Kang 001 (IEICE Electron. Express, 2012)

An accurate diagnosis of transition fault clusters based on single fault simulation. - Yoseop Lim; Jaeseok Park; Sungho Kang 001 (IEICE Electron. Express, 2012)

A Die Selection and Matching Method with Two Stages for Yield Enhancement of 3-D Memories. - Wooheon Kang; Changwook Lee; Keewon Cho; Sungho Kang 001 (Asian Test Symposium, 2013)

Thermal-aware dynamic voltage frequency scaling for many-core processors under process variations. - Hyejeong Hong; Jaeil Lim; Hyunyul Lim; Sungho Kang 001 (IEICE Electron. Express, 2013)

Dynamic thermal management for 3D multicore processors under process variations. - Hyejeong Hong; Jaeil Lim; Hyunyul Lim; Sungho Kang 001 (IEICE Electron. Express, 2013)

Acceleration of Deep Packet Inspection Using a Multi-Byte Processing Prefilter. - Hyejeong Hong; Sungho Kang 001 (IEICE Trans. Commun., 2013)

Built-In Self-Test for Static ADC Testing with a Triangle-Wave. - Incheol Kim; Ingeol Lee; Sungho Kang 001 (IEICE Trans. Electron., 2013)

A Scalable and Parallel Test Access Strategy for NoC-Based Multicore System. - Taewoo Han; Inhyuk Choi; Hyunggoy Oh; Sungho Kang 001 (ATS, 2014)

Recovery-enhancing task scheduling for multicore processors under NBTI impact. - Hyejeong Hong; Jaeil Lim; Sungho Kang 001 (IEICE Electron. Express, 2014)

A New Fuse Architecture and a New Post-Share Redundancy Scheme for Yield Enhancement in 3-D-Stacked Memories. - Changwook Lee; Wooheon Kang; Donkoo Cho; Sungho Kang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

A BIRA for Memories With an Optimal Repair Rate Using Spare Memories for Area Reduction. - Wooheon Kang; Hyungjun Cho; Joohwan Lee; Sungho Kang 001 (IEEE Trans. Very Large Scale Integr. Syst., 2014)

A Delay Test Architecture for TSV With Resistive Open Defects in 3-D Stacked Memories. - Hyungsu Sung; Keewon Cho; Kunsang Yoon; Sungho Kang 001 (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Scan Chain Reordering-Aware X-Filling and Stitching for Scan Shift Power Reduction. - Sungyoul Seo; Yong Lee 002; Hyeonchan Lim; Joohwan Lee; Hongbom Yoo; Yojoung Kim; Sungho Kang 001 (ATS, 2015)

Near optimal repair rate built-in redundancy analysis with very small hardware overhead. - Woosung Lee; Keewon Cho; Jooyoung Kim; Sungho Kang 001 (ISQED, 2015)

Low power scan bypass technique with test data reduction. - Hyunyul Lim; Wooheon Kang; Sungyoul Seo; Yong Lee 002; Sungho Kang 001 (ISQED, 2015)

A scan shifting method based on clock gating of multiple groups for low power scan testing. - Sungyoul Seo; Yong Lee 002; Joohwan Lee; Sungho Kang 001 (ISQED, 2015)

Lifetime Reliability Enhancement of Microprocessors: Mitigating the Impact of Negative Bias Temperature Instability. - Hyejeong Hong; Jaeil Lim; Hyunyul Lim; Sungho Kang 001 (ACM Comput. Surv., 2015)

Reduced-code test method using sub-histograms for pipelined ADCs. - HyeonUk Son; Jaewon Jang; Heetae Kim; Sungho Kang 001 (IEICE Electron. Express, 2015)

Eco Assist Techniques through Real-time Monitoring of BEV Energy Usage Efficiency. - Younsun Kim; Ingeol Lee; Sungho Kang 001 (Sensors, 2015)

3-D Stacked DRAM Refresh Management With Guaranteed Data Reliability. - Jaeil Lim; Hyunyul Lim; Sungho Kang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

A 3 Dimensional Built-In Self-Repair Scheme for Yield Improvement of 3 Dimensional Memories. - Wooheon Kang; Changwook Lee; Hyunyul Lim; Sungho Kang 001 (IEEE Trans. Reliab., 2015)

A Novel Massively Parallel Testing Method Using Multi-Root for High Reliability. - Haksong Kim; Yong Lee 002; Sungho Kang 001 (IEEE Trans. Reliab., 2015)

Majority-Based Test Access Mechanism for Parallel Testing of Multiple Identical Cores. - Taewoo Han; Inhyuk Choi; Sungho Kang 001 (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Test access mechaism for stack test time reduction of 3-dimensional integrated circuit. - Inhyuk Choi; Hyunggoy Oh; Sungho Kang 001 (APCCAS, 2016)

A new online test and debug methodology for automotive camera image processing system. - Hyunggoy Oh; Inhyuk Choi; Sungho Kang 001 (APCCAS, 2016)

Discussion of cost-effective redundancy architectures. - Keewon Cho; Jooyoung Kim; Hayoung Lee; Sungho Kang 001 (ISOCC, 2016)

Software-based embedded core test using multi-polynomial for test data reduction. - Soyeon Kang; Inhyuk Choi; Hyeonchan Lim; Sungyoul Seo; Sungho Kang 001 (ISOCC, 2016)

Process variation-aware bridge fault analysis. - Heetae Kim; Inhyuk Choi; Jaeil Lim; Hyunggoy Oh; Sungho Kang 001 (ISOCC, 2016)

A test methodology to screen scan-path failures. - Junghwan Kim; Young-Woo Lee; Minho Cheong; Sungyoul Seo; Sungho Kang 001 (ISOCC, 2016)

P-backtracking: A new scan chain diagnosis method with probability. - Tae Hyun Kim; Hyunyul Lim; Sungho Kang 001 (ISOCC, 2016)

A Survey of Repair Analysis Algorithms for Memories. - Keewon Cho; Wooheon Kang; Hyungjun Cho; Changwook Lee; Sungho Kang 001 (ACM Comput. Surv., 2016)

Parallelized Network-on-Chip-Reused Test Access Mechanism for Multiple Identical Cores. - Taewoo Han; Inhyuk Choi; Hyunggoy Oh; Sungho Kang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

A New 3-D Fuse Architecture to Improve Yield of 3-D Memories. - Wooheon Kang; Changwook Lee; Hyunyul Lim; Sungho Kang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

Tri-State Coding Using Reconfiguration of Twisted Ring Counter for Test Data Compression. - Sungyoul Seo; Yong Lee 002; Sungho Kang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

Optimized Built-In Self-Repair for Multiple Memories. - Wooheon Kang; Changwook Lee; Hyunyul Lim; Sungho Kang 001 (IEEE Trans. Very Large Scale Integr. Syst., 2016)

An efficient built-in self-repair scheme for area reduction. - Keewon Cho; Young-Woo Lee; Sungyoul Seo; Sungho Kang 001 (ISOCC, 2017)

A new repair scheme for TSV-based 3D memory using base die repair cells. - Donghyun Han; Hayoung Lee; Donghyun Kim; Sungho Kang 001 (ISOCC, 2017)

Test data reduction method based on berlekamp-massey algorithm. - Hyeonchan Lim; Junghwan Kim; Soyeon Kang; Sungho Kang 001 (ISOCC, 2017)

LARECD: Low area overhead and reliable error correction DMR architecture. - Hyunyul Lim; Tae Hyun Kim; Dongsu Lee; Sungho Kang 001 (ISOCC, 2017)

A selective error data capture method using on-chip DRAM for silicon debug of multi-core design. - Hyunggoy Oh; Heetae Kim; Jaeil Lim; Sungho Kang 001 (ISOCC, 2017)

Broadcast scan compression based on deterministic pattern generation algorithm. - Hyeonchan Lim; Sungyoul Seo; Soyeon Kang; Sungho Kang 001 (ISQED, 2017)

Off-chip test architecture for improving multi-site testing efficiency using tri-state decoder and 3V-level encoder. - Sungyoul Seo; Hyeonchan Lim; Soyeon Kang; Sungho Kang 001 (ISQED, 2017)

A novel X-filling method for capture power reduction. - Heetae Kim; Hyunggoy Oh; Jaeil Lim; Sungho Kang 001 (IEICE Electron. Express, 2017)

Reconfigurable scan architecture for test power and data volume reduction. - Hyunggoy Oh; Heetae Kim; Jaeil Lim; Sungho Kang 001 (IEICE Electron. Express, 2017)

Proof of Concept of Home IoT Connected Vehicles. - Younsun Kim; Hyunggoy Oh; Sungho Kang 001 (Sensors, 2017)

DRAM-Based Error Detection Method to Reduce the Post-Silicon Debug Time for Multiple Identical Cores. - Hyunggoy Oh; Inhyuk Choi; Sungho Kang 001 (IEEE Trans. Computers, 2017)

An On-Chip Error Detection Method to Reduce the Post-Silicon Debug Time. - Hyunggoy Oh; Taewoo Han; Inhyuk Choi; Sungho Kang 001 (IEEE Trans. Computers, 2017)

Grouping-Based TSV Test Architecture for Resistive Open and Bridge Defects in 3-D-ICs. - Young-Woo Lee; Hyeonchan Lim; Sungho Kang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

FRESH: A New Test Result Extraction Scheme for Fast TSV Tests. - Jaeseok Park; Hyunyul Lim; Sungho Kang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

R2-TSV: A Repairable and Reliable TSV Set Structure Reutilizing Redundancies. - Jaeseok Park; Minho Cheong; Sungho Kang 001 (IEEE Trans. Reliab., 2017)

Chain-Based Approach for Fast Through-Silicon-Via Coupling Delay Estimation. - Jaewon Jang; Minho Cheong; Jin-Ho Ahn; Sung Kyu Lim; Sungho Kang 001 (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Hardware-Efficient Built-In Redundancy Analysis for Memory With Various Spares. - Jooyoung Kim; Woosung Lee; Keewon Cho; Sungho Kang 001 (IEEE Trans. Very Large Scale Integr. Syst., 2017)

A Test Methodology for Neural Computing Unit. - Minho Cheong; Ingeol Lee; Sungho Kang 001 (ISOCC, 2018)

2-D Failure Bitmap Compression Using Line Fault Marking Method. - Keewon Cho; Young-Woo Lee; Sungyoul Seo; Sungho Kang 001 (ISOCC, 2018)

Low Power Scan Chain Architecture Based on Circuit Topology. - Heetae Kim; Hyunggoy Oh; Sangjun Lee; Sungho Kang 001 (ISOCC, 2018)

A Software-based Scan Chain Diagnosis for Double Faults in A Scan Chain. - Hyeonchan Lim; Seokjun Jang; Sungho Kang 001 (ISOCC, 2018)

Dynamic voltage Drop induced Path Delay Analysis for STV and NTV Circuits during At-speed Scan Test. - Hyunggoy Oh; Heetae Kim; Sangjun Lee; Sungho Kang 001 (ISOCC, 2018)

3D Memory Formed of Unrepairable Memory Dice and Spare Layer. - Donghyun Han; Hayoung Lee; Seungtaek Lee; Minho Moon; Sungho Kang 001 (TENCON, 2018)

Neural Network Reliability Enhancement Approach Using Dropout Underutilization in GPU. - Dongsu Lee; Hyunyul Lim; Tae Hyun Kim; Sungho Kang 001 (TENCON, 2018)

A Statistic-Based Scan Chain Reordering for Energy-Quality Scalable Scan Test. - Sungyoul Seo; Keewon Cho; Young-Woo Lee; Sungho Kang 001 (IEEE J. Emerg. Sel. Topics Circuits Syst., 2018)

Test Resource Reused Debug Scheme to Reduce the Post-Silicon Debug Cost. - Inhyuk Choi; Hyunggoy Oh; Young-Woo Lee; Sungho Kang 001 (IEEE Trans. Computers, 2018)

Fault Group Pattern Matching With Efficient Early Termination for High-Speed Redundancy Analysis. - Hayoung Lee; Kiwon Cho; Donghyun Kim; Sungho Kang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Thermal Aware Test Scheduling for NTV Circuit. - Jaeil Lim; Hyunggoy Oh; Heetae Kim; Sungho Kang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Fast Built-In Redundancy Analysis Based on Sequential Spare Line Allocation. - Hayoung Lee; Jooyoung Kim; Keewon Cho; Sungho Kang 001 (IEEE Trans. Reliab., 2018)

An Area-Efficient BIRA With 1-D Spare Segments. - Donghyun Kim; Hayoung Lee; Sungho Kang 001 (IEEE Trans. Very Large Scale Integr. Syst., 2018)

A Hardware-efficient TSV Repair Scheme Based on Butterfly Topology. - Minho Cheng; Hyunyul Lim; Tae Hyun Kim; Sungho Kang 001 (ISOCC, 2019)

A New Scan Chain Reordering Method for Low Power Consumption based on Care Bit Density. - Kyunghwan Cho; Jihye Kim 002; Hyunggoy Oh; Sangjun Lee; Sungho Kang 001 (ISOCC, 2019)

Transition-delay Test Methodology for Designs with Self-gating. - Jihye Kim 002; Sangjun Lee; Minho Moon; Sungho Kang 001 (ISOCC, 2019)

Redundancy Analysis based on Fault Distribution for Memory with Complex Spares. - Hayoung Lee; Donghyun Han; Seungtaek Lee; Sungho Kang 001 (ISOCC, 2019)

Tunable Compact Probing Detector with Fast Analysis Time Against Invasive Attacks. - Young-Woo Lee; Youngkwang Lee; Minho Moon; Sungho Kang 001 (ISOCC, 2019)

An Efficient BIRA Utilizing Characteristics of Spare Pivot Faults. - Keewon Cho; Young-Woo Lee; Sungyoul Seo; Sungho Kang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

TSV Repair Architecture for Clustered Faults. - Jaewon Jang; Minho Cheong; Sungho Kang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

Highly Reliable Redundant TSV Architecture for Clustered Faults. - Ingeol Lee; Minho Cheong; Sungho Kang 001 (IEEE Trans. Reliab., 2019)

Test-Friendly Data-Selectable Self-Gating (DSSG). - Jihye Kim 002; Sangjun Lee; Sungho Kang 001 (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Dynamic Built-In Redundancy Analysis for Memory Repair. - Hayoung Lee; Donghyun Han; Seungtaek Lee; Sungho Kang 001 (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Memory-like Defect Diagnosis for CMOL FPGAs. - Jihye Kim 002; Hayoung Lee; Seokjun Jang; Hogyeong Kim; Sungho Kang 001 (ISOCC, 2020)

Redundancy Analysis Optimization with Clustered Known Solutions for High Speed Repair. - Hayoung Lee; Donghyun Han; Hogyeong Kim; Sungho Kang 001 (ISOCC, 2020)

Diagnosis of Scan Chain Faults Based-on Machine-Learning. - Hyeonchan Lim; Tae Hyun Kim; Seunghwan Kim; Sungho Kang 001 (ISOCC, 2020)

W-ERA: One-Time Memory Repair with Wafer-Level Early Repair Analysis for Cost Reduction. - Hayoung Lee; Donghyun Han; Hogyeong Kim; Sungho Kang 001 (ITC-Asia, 2020)

Fail Memory Configuration Set for RA Estimation. - Hayoung Lee; Keewon Cho; Sungho Kang 001; Wooheon Kang; Seungtaek Lee; Woosik Jeong (ITC, 2020)

Fine-Grained Defect Diagnosis for CMOL FPGA Circuits. - Jihye Kim 002; Hayoung Lee; Seokjun Jang; Sungho Kang 001 (IEEE Access, 2020)

Scan-Chain-Fault Diagnosis Using Regressions in Cryptographic Chips for Wireless Sensor Networks. - Hyunyul Lim; Minho Cheong; Sungho Kang 001 (Sensors, 2020)

A 3-D Rotation-Based Through-Silicon via Redundancy Architecture for Clustering Faults. - Minho Cheong; Ingeol Lee; Sungho Kang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Robust Secure Shield Architecture for Detection and Protection Against Invasive Attacks. - Young-Woo Lee; Hyeonchan Lim; Youngkwang Lee; Sungho Kang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

A New Logic Topology-Based Scan Chain Stitching for Test-Power Reduction. - Sangjun Lee; Kyunghwan Cho; Sungki Choi; Sungho Kang 001 (IEEE Trans. Circuits Syst., 2020)

GPU-Based Redundancy Analysis Using Concurrent Evaluation. - Tae Hyun Kim; Hayoung Lee; Sungho Kang 001 (IEEE Trans. Very Large Scale Integr. Syst., 2020)

Hardware Efficient Built-in Self-test Architecture for Power and Ground TSVs in 3D IC. - Donghyun Han; Youngkwang Lee; Sooryeong Lee; Sungho Kang 001 (ISOCC, 2021)

Secure Scan Design through Pseudo Fault Injection. - Seokjun Jang; Hyungil Woo; Sunghoon Kim; Sungho Kang 001 (ISOCC, 2021)

A Circular-based TSV Repair Architecture. - Youngkwang Lee; Donghyun Han; Sooryeong Lee; Sungho Kang 001 (ISOCC, 2021)

Hybrid Test Access Mechanism for Multiple Identical Cores. - Sangjun Lee; Jongho Park; Inhwan Lee; Kwonhyoung Lee; Sungho Kang 001 (ISOCC, 2021)

Area Efficient Built-In Redundancy Analysis using Pre-Solutions with Various Spare Structure. - Youngki Moon; Hyunho Yoo; Donghyun Han; Sungho Kang 001 (ISOCC, 2021)

An Effective Spare Allocation Methodology for 3D Memory Repair with BIRA. - Seung Ho Shin; Hayoung Lee; Younwoo Yoo; Sungho Kang 001 (ISOCC, 2021)

Post-bond Repair of Line Faults with Double-bit ECC for 3D Memory. - Younwoo Yoo; Hayoung Lee; Seung Ho Shin; Sungho Kang 001 (ISOCC, 2021)

Effective Spare Line Allocation Built-in Redundancy Analysis With Base Common Spare for Yield Improvement of 3D Memory. - Donghyun Han; Hayoung Lee; Sungho Kang 001 (IEEE Access, 2021)

ECC-Aware Fast and Reliable Pattern Matching Redundancy Analysis for Highly Reliable Memory. - Donghyun Han; Hayoung Lee; Seungtaek Lee; Sungho Kang 001 (IEEE Access, 2021)

Reconfigurable Scan Architecture for High Diagnostic Resolution. - Seokjun Jang; Jihye Kim 002; Sungho Kang 001 (IEEE Access, 2021)

A Low-Power BIST Scheme Using Weight-Aware Scan Grouping and Scheduling for Automotive ICs. - Kwonhyoung Lee; Sangjun Lee; Jongho Park; Inhwan Lee; Sungho Kang 001 (IEEE Access, 2021)

On-Chip Error Detection Reusing Built-In Self-Repair for Silicon Debug. - Hayoung Lee; Hyunggoy Oh; Sungho Kang 001 (IEEE Access, 2021)

An In-DRAM BIST for 16 Gb DDR4 DRAM in the 2nd 10-nm-Class DRAM Process. - Jaewon Park; Jae Hoon Lee; Sang-Kil Park; Ki Chul Chun; Kyomin Sohn; Sungho Kang 001 (IEEE Access, 2021)

A Secure Scan Architecture Protecting Scan Test and Scan Dump Using Skew-Based Lock and Key. - Hyungil Woo; Seokjun Jang; Sungho Kang 001 (IEEE Access, 2021)

Low-Power Scan Correlation-Aware Scan Cluster Reordering for Wireless Sensor Networks. - Sangjun Lee; Kyunghwan Cho; Jihye Kim 002; Jongho Park; Inhwan Lee; Sungho Kang 001 (Sensors, 2021)

Enhanced Postbond Test Architecture for Bridge Defects Between the TSVs. - Jungil Mok; Hyeonchan Lim; Sungho Kang 001 (IEEE Trans. Very Large Scale Integr. Syst., 2021)

Pair-Grouping Scan Chain Architecture for Multiple Scan Cell Fault Diagnosis. - Sunghoon Kim; Seokjun Jang; Youngki Moon; Sungho Kang 001 (ISOCC, 2022)

Logic Diagnosis Based on Deep Learning for Multiple Faults. - Tae Hyun Kim; Hyeonchan Lim; Minho Cheong; Hyojoon Yun; Sungho Kang 001 (ISOCC, 2022)

ZOS: Zero Overhead Scan for Systolic Array-based AI accelerator. - Jihye Kim 002; Hayoung Lee; Jongho Park; Sungho Kang 001 (ISOCC, 2022)

PROG: Per-Row Output Generator for BOST. - Sooryeong Lee; Hayoung Lee; Younwoo Yoo; Seung Ho Shin; Sungho Kang 001 (ISOCC, 2022)

FAME: Fault Address Memory Structure for Repair Time Reduction. - Hayoung Lee; Sooryeong Lee; Younwoo Yoo; Seung Ho Shin; Sungho Kang 001 (ISOCC, 2022)

Cell-Aware Scan Diagnosis Using Partially Synchronous Set and Reset. - Hyeonchan Lim; Hyojoon Yun; Juyong Lee; Sungho Kang 001 (ISOCC, 2022)

Correlation Aware Random Pattern Generation for Test Time and Shift Power Reduction of Logic BIST. - Jongho Park; Sangjun Lee; Inhwan Lee; Sungwhan Park; Sungho Kang 001 (ISOCC, 2022)

An Improved Early Termination Methodology Using Convolutional Neural Network. - Seung Ho Shin; Hayoung Lee; Sooryeong Lee; Younwoo Yoo; Sungho Kang 001 (ISOCC, 2022)

SPAR: A New Test-Point Insertion Using Shared Points for Area Overhead Reduction. - Gyungbin Kim; Minho Cheong; Sungho Kang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Multibank Optimized Redundancy Analysis Using Efficient Fault Collection. - Hogyeong Kim; Hayoung Lee; Donghyun Han; Sungho Kang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Reduced-Pin-Count BOST for Test-Cost Reduction. - Youngkwang Lee; Young-Woo Lee; Sungyoul Seo; Sungho Kang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

A Hybrid Test Scheme for Automotive IC in Multisite Testing. - Hyeonchan Lim; Hyojoon Yun; Sungho Kang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Herringbone-Based TSV Architecture for Clustered Fault Repair and Aging Recovery. - Sangmin Park; Minho Cheong; Donghyun Han; Sungho Kang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Scan Cell Modification for Intra Cell-Aware Scan Chain Diagnosis. - Hyeonchan Lim; Hyojoon Yun; Sungho Kang 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

ECMO: ECC Architecture Reusing Content-Addressable Memories for Obtaining High Reliability in DRAM. - Hayoung Lee; Younwoo Yoo; Seung Ho Shin; Sungho Kang 001 (IEEE Trans. Very Large Scale Integr. Syst., 2022)

LOTS: Low Overhead TSV Repair Method Using IEEE-1838 Standard Architecture. - Sunghoon Kim; Donghyun Han; Seokjun Jang; Sungho Kang 001 (ISOCC, 2023)

A New Flip-flop Shared Architecture of Test Point Insertion for Scan Design. - Hyemin Kim; Sangjun Lee; Jongho Park; Sungwhan Park; Sungho Kang 001 (ISOCC, 2023)

Redundancy Analysis Simplification Scheme for High-Speed Memory Repair. - Hayoung Lee; Younwoo Yoo; Seung Ho Shin; Sungho Kang 001 (ISOCC, 2023)

GPU-Based Redundancy Analysis using Partitioning Method for Memory Repair. - Younwoo Yoo; Hayoung Lee; Seung Ho Shin; Sungho Kang 001 (ISOCC, 2023)

Machine Learning based Scan Chain Diagnosis for Double Faults. - Hyojoon Yun; Tae-Hyun Kim; Sungho Kang 001 (ISOCC, 2023)

Scan Chain Architecture With Data Duplication for Multiple Scan Cell Fault Diagnosis. - Sunghoon Kim; Seokjun Jang; Sungho Kang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Novel Error-Tolerant Voltage-Divider-Based Through-Silicon-Via Test Architecture. - Youngkwang Lee; Donghyun Han; Sooryeong Lee; Sungho Kang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Shift Left Quality Management System (QMS) Using a 3-D Matrix Scanning Method on System on a Chip. - Yong Lee 002; Seokjun Jang; Sungho Kang 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

TSV Built-In Self-Repair Architecture for Improving the Yield and Reliability of HBM. - Youngkwang Lee; Donghyun Han; Sungho Kang 001 (IEEE Trans. Very Large Scale Integr. Syst., 2023)

TRUST: Through-Silicon via Repair Using Switch Matrix Topology. - Hayoung Lee; Seung Ho Shin; Younwoo Yoo; Sungho Kang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

STRAIT: Self-Test and Self-Recovery for AI Accelerator. - Hayoung Lee; Jihye Kim 002; Jongho Park; Sungho Kang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Signal Shifting-based Reusable Redundant TSV Structure for Infrastructure TSV. - Donghyun Han; Sunghoon Kim; Sungho Kang 001 (ISOCC, 2024)

Scan Architecture with Data Observation for Multiple Scan Cell Fault Diagnosis. - Juyong Lee; Sooryeong Lee; Hayoung Lee; Sungho Kang 001 (ISOCC, 2024)

APAPG: Address Pre-Processed ALPG for High-Speed Linear Test. - Sooryeong Lee; Hayoung Lee; Juyong Lee; Sungho Kang 001 (ISOCC, 2024)

Effective Data-Width Aware ECC Scheme for HBM. - Seung Ho Shin; Youngki Moon; Byungsoo Kim; Sungho Kang 001 (ISOCC, 2024)

An Efficient Scan Diagnosis for Intermittent Faults Using CNN With Multi-Channel Data. - Hyojoon Yun; Hyeonchan Lim; Hayoung Lee; Doohyun Yoon; Sungho Kang 001 (IEEE Access, 2024)

A New Fail Address Memory Architecture for Cost-Effective ATE. - Hayoung Lee; Sooryeong Lee; Sungho Kang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

Reconfigurable Multi-Bit Scan Flip-Flop for Cell-Aware Diagnosis. - Hyeonchan Lim; Tae-Hyun Kim; Sungho Kang 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A New Zero-Overhead Test Method for Low-Power AI Accelerators. - Sangjun Lee; Jongho Park; Sungwhan Park; Hyemin Kim; Sungho Kang 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

RA-Aware Fail Data Collection Architecture for Cost Reduction. - Hayoung Lee; Sooryeong Lee; Sungho Kang 001 (IEEE Trans. Very Large Scale Integr. Syst., 2024)

A New ISA for High-Speed and Area-Efficient ALPG. - Juyong Lee; Hayoung Lee; Sooryeong Lee; Sungho Kang 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

GRAP: Efficient GPU-Based Redundancy Analysis Using Parallel Evaluation for Cross Faults. - Seung Ho Shin; Hayoung Lee; Sungho Kang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

An Area-Efficient Systolic Array Redundancy Architecture for Reliable AI Accelerator. - Hayoung Lee; Jongho Park; Sungho Kang 001 (IEEE Trans. Very Large Scale Integr. Syst., 2024)

Low Cost TSV Repair Architecture Using Switch-Based Matrix for Highly Clustered Faults. - Seokjun Jang; Donghyun Han; Sunghoon Kim; Dayoung Kim; Sungho Kang 001 (IEEE Access, 2025)

A New Test Point Insertion Using Weight Adjusted Grouping. - Jaehyun Kim; Hyemin Kim; Jongho Park; Sangjun Lee; Sungho Kang 001 (IEEE Access, 2025)

RAPID: Redundancy Analysis With Parallelized and Intelligent Distribution. - Younwoo Yoo; Hayoung Lee; Seung Ho Shin; Sungho Kang 001 (IEEE Access, 2025)

PASS: Pattern-Sequence-Authentication-Based Secure Scan Against Reverse Engineering Attacks. - Seokjun Jang; Youngki Moon; Duyeon Won; Sungho Kang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

PETRA: Powerful Early Termination-Based Redundancy Analysis. - Youngkwang Lee; Hyojun Yun; Younwoo Yoo; Sungho Kang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

A New Pipelined Output Data Reducer of BOST for Improved Parallelism. - Sooryeong Lee; Hayoung Lee; Juyong Lee; Sungho Kang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

A Novel Prediction-Based Two-Tiered ECC for Mitigating SWD Errors in HBM. - Youngki Moon; Seung Ho Shin; Seokjun Jang; Duyeon Won; Sungho Kang 001 (IEEE Trans. Very Large Scale Integr. Syst., 2025)

Effective Parallel Redundancy Analysis Using GPU for Memory Repair. - Seung Ho Shin; Hayoung Lee; Sungho Kang 001 (IEEE Trans. Very Large Scale Integr. Syst., 2025)

An Efficient Low-Power BIST for Automotive SoC With Periodic Pattern Type Selection. - Jongho Park; Sangjun Lee; Hyemin Kim; Jaeyoung Joung; Jaehyun Kim; Sungho Kang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

SPOT: Fast and Optimal Built-In Redundancy Analysis Using Smart Potential Case Collection. - Donghyun Han; Sunghoon Kim; Dayoung Kim; Sungho Kang 001 (IEEE Trans. Very Large Scale Integr. Syst., 2025)

A Cost-Effective Per-Pin ALPG for High-Speed Memory Testing. - Juyong Lee; Hayoung Lee; Sooryeong Lee; Sungho Kang 001 (IEEE Trans. Very Large Scale Integr. Syst., 2025)

A Robust Test Architecture for Low-Power AI Accelerators. - Hayoung Lee; Juyong Lee; Sungho Kang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

A Built-In Self-Repair With Maximum Fault Collection and Fast Analysis Method for HBM. - Joonsik Yoon; Hayoung Lee; Youngki Moon; Seung Ho Shin; Sungho Kang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

An Efficient Test Architecture Using Hybrid Built-In Self-Test for Processing-in-Memory. - Hayoung Lee; Juyong Lee; Sungho Kang 001 (IEEE Trans. Very Large Scale Integr. Syst., 2025)

A Novel CNN-Based Redundancy Analysis Using Parallel Solution Decision. - Seung Ho Shin; Minho Cheong; Hayoung Lee; Byungsoo Kim; Sungho Kang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)