Differential Pass Transistor Pulsed Latch. - Moo-young Kim; Inhwa Jung; Young-Ho Kwak; Sunghoon Ahn; Chulwoo Kim (SoCC, 2005)

A 1.5 GHz spread spectrum clock generator with a 5000ppm piecewise linear modulation. - Minyoung Song; Sunghoon Ahn; Inhwa Jung; Yongtae Kim; Chulwoo Kim (CICC, 2008)

A 10MHz to 315MHz cascaded hybrid PLL with piecewise linear calibrated TDC. - Minyoung Song; Young-Ho Kwak; Sunghoon Ahn; Wooseok Kim; ByeongHa Park; Chulwoo Kim (CICC, 2009)

A 32Gb MLC NAND-flash memory with Vth-endurance-enhancing schemes in 32nm CMOS. - Changhyuk Lee; Sok-Kyu Lee; Sunghoon Ahn; Jinhaeng Lee; Wonsun Park; Yongdeok Cho; Chaekyu Jang; Chulwoo Yang; Sanghwa Chung; In-Suk Yun; Byoungin Joo; Byoungkwan Jeong; et al. (ISSCC, 2010)

A 32-Gb MLC NAND Flash Memory With Vth Endurance Enhancing Schemes in 32 nm CMOS. - Changhyuk Lee; Sok-Kyu Lee; Sunghoon Ahn; Jinhaeng Lee; Wonsun Park; Yongdeok Cho; Chaekyu Jang; Chulwoo Yang; Sanghwa Chung; In-Suk Yun; Byoungin Joo; Byoungkwan Jeong; et al. (IEEE J. Solid State Circuits, 2011)

Piecewise Linear Modulation Technique for Spread Spectrum Clock Generation. - Minyoung Song; Sunghoon Ahn; Inhwa Jung; Yongtae Kim; Chulwoo Kim (IEEE Trans. Very Large Scale Integr. Syst., 2013)

10-315-MHz Cascaded Hybrid Phase-Locked Loop for Pixel Clock Generation. - Minyoung Song; Young-Ho Kwak; Sunghoon Ahn; Hojin Park; Chulwoo Kim (IEEE Trans. Very Large Scale Integr. Syst., 2013)

19.2 A 93.4mm2 64Gb MLC NAND-flash memory with 16nm CMOS technology. - Sungdae Choi; Duckju Kim; Sungwook Choi; Byungryul Kim; Sunghyun Jung; Kichang Chun; Namkyeong Kim; Wanseob Lee; Taisik Shin; Hyunjong Jin; Hyunchul Cho; Sunghoon Ahn; et al. (ISSCC, 2014)