A Low-Jitter Open-Loop All-Digital Clock Generator with 2 Cycle Lock-Time. - Moo-young Kim; Dongsuk Shin; Hyunsoo Chae; Sunghwa Ok; Chulwoo Kim (CICC, 2007)

A DC-DC converter with a dual VCDL-based ADC and a self-calibrated DLL-based clock generator for an energy-aware EISC processor. - Sunghwa Ok; Jungmoon Kim; Gilwon Yoon; Hyunho Chu; Jaegeun Oh; Seon Wook Kim; Chulwoo Kim (CICC, 2008)

A Low-Power Programmable DLL-Based Clock Generator With Wide-Range Antiharmonic Lock. - Jabeom Koo; Sunghwa Ok; Chulwoo Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2009)

An Antiharmonic, Programmable, DLL-Based Frequency Multiplier for Dynamic Frequency Scaling. - Sunghwa Ok; Kyunghoon Chung; Jabeom Koo; Chulwoo Kim (IEEE Trans. Very Large Scale Integr. Syst., 2010)

A 1.2V 38nm 2.4Gb/s/pin 2Gb DDR4 SDRAM with bank group and ×4 half-page architecture. - Kibong Koo; Sunghwa Ok; Yonggu Kang; Seungbong Kim; Choungki Song; Hyeyoung Lee; Hyungsoo Kim; Yongmi Kim; Jeonghun Lee; Seunghan Oak; Yosep Lee; Jungyu Lee 002; et al. (ISSCC, 2012)

13.2 A 1Tb 4b/Cell 96-Stacked-WL 3D NAND Flash Memory with 30MB/s Program Throughput Using Peripheral Circuit Under Memory Cell Array Technique. - Hwang Huh; Wanik Cho; Jinhaeng Lee; Yujong Noh; Yongsoon Park; Sunghwa Ok; Jongwoo Kim; Kayoung Cho; Hyunchul Lee; Geonu Kim; Kangwoo Park; Kwanho Kim; et al. (ISSCC, 2020)

A 176-Stacked 512Gb 3b/Cell 3D-NAND Flash with 10.8Gb/mm2 Density with a Peripheral Circuit Under Cell Array Architecture. - Jae-Woo Park; Doogon Kim; Sunghwa Ok; Jaebeom Park; Taeheui Kwon; Hyunsoo Lee; Sungmook Lim; Sunyoung Jung; Hyeong-Jin Choi; Taikyu Kang; Gwan Park; Chul-Woo Yang; et al. (ISSCC, 2021)

A 321-Layer 2Tb 4b/cell 3D-NAND-Flash Memory with a 75MB/s Program Throughput. - Wanik Cho; Chanhui Jeong; Jongwoo Kim; Jongseok Jung; Keunseon Ahn; Jayoon Goo; Sangkyu Lee; Kayoung Cho; Tei Cho; Dauni Kim; Gwan Park; Yushin Ahn; et al. (ISSCC, 2025)