0.293-mm2 Fast Transient Response Hysteretic Quasi-V2 DC-DC Converter With Area-Efficient Time-Domain-Based Controller in 0.35-µm CMOS. - Dong-Hoon Jung; Ki-Ryong Kim; Sunghwan Jo; Seong-Ook Jung (IEEE J. Solid State Circuits, 2018)

CNN Acceleration With Hardware-Efficient Dataflow for Super-Resolution. - Sumin Lee; Sunghwan Jo; Hong Keun Ahn; Seong-Ook Jung (IEEE Access, 2020)

A 5 Gb/s Time-Interleaved Voltage-Mode Duobinary Encoding Scheme for 3-D-Stacked IC. - Ji-Young Kim; Jongsoo Lee; Ki-Ryong Kim; Sunghwan Jo; Byoung-Mo Moon; Kyomin Sohn; Seong-Ook Jung (IEEE J. Solid State Circuits, 2022)

A 16 GB 1024 GB/s HBM3 DRAM With Source-Synchronized Bus Design and On-Die Error Control Scheme for Enhanced RAS Features. - Yesin Ryu; Sung-Gi Ahn; Jaehoon Lee 005; Jaewon Park; Yong-Ki Kim; Hyochang Kim; Yeong Geol Song; Han-Won Cho; Sunghye Cho; Seung Ho Song; Haesuk Lee; Useung Shin; et al. (IEEE J. Solid State Circuits, 2023)