A Design of A Processor Architecture for Codes With Explicit Data Dependencies. - Sunghyun Jee; Sukil Kim (PP, 2001)

Dynamically Scheduling VLIW Instructions with Dependency Information. - Sunghyun Jee; Kannappan Palaniappan (Interaction between Compilers and Computer Architectures, 2002)

Compiler Processor Tradeoffs for DISVLIW Architecture. - Sunghyun Jee; Kannappan Palaniappan (ISPAN, 2002)

Performance evaluation for a compressed-VLIW processor. - Sunghyun Jee; Kannappan Palaniappan (SAC, 2002)

Performance of dynamically scheduling VLIW instructions. - Sunghyun Jee; Kannappan Palaniappan (SoC, 2003)