Design techniques for high performance CMOS flash analog-to-digital converters. - Sunghyun Park 006; Michael P. Flynn (ECCTD, 2005)

A 3.5 GS/s 5-b Flash ADC in 90 nm CMOS. - Sunghyun Park 006; Yorgos Palaskas; Ashoke Ravi; Ralph E. Bishop; Michael P. Flynn (CICC, 2006)

A 4GS/s 4b Flash ADC in 0.18µm CMOS. - Sunghyun Park 006; Yorgos Palaskas; Michael P. Flynn (ISSCC, 2006)

A regenerative comparator structure with integrated inductors. - Sunghyun Park 006; Michael P. Flynn (IEEE Trans. Circuits Syst. I Regul. Pap., 2006)

A 4-GS/s 4-bit Flash ADC in 0.18-µm CMOS. - Sunghyun Park 006; Yorgos Palaskas; Michael P. Flynn (IEEE J. Solid State Circuits, 2007)

A 9Gbit/s serial transceiver for on-chip global signaling over lossy transmission lines. - JunYoung Park; Joshua Jaeyoung Kang; Sunghyun Park 006; Michael P. Flynn (CICC, 2008)

A 2.5 mW 80 dB DR 36 dB SNDR 22 MS/s Logarithmic Pipeline ADC. - Jongwoo Lee; Joshua Jaeyoung Kang; Sunghyun Park 006; Jae-sun Seo; Jens Anders; Jorge Guilherme; Michael P. Flynn (IEEE J. Solid State Circuits, 2009)

A 9-Gbit/s Serial Transceiver for On-Chip Global Signaling Over Lossy Transmission Lines. - JunYoung Park; Joshua Jaeyoung Kang; Sunghyun Park 006; Michael P. Flynn (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)