A 4266 Mb/s/pin LPDDR4 Interface With An Asynchronous Feedback CTLE and An Adaptive 3-Step Eye Detection Algorithm for Memory Controller. - Mino Kim; Joo-Hyung Chae; Sungphil Choi; Gi-Moon Hong; Hyeongjun Ko; Deog-Kyoon Jeong; Suhwan Kim 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

A Low-Power and Low-Noise 20: 1 Serializer with Two Calibration Loops in 55-nm CMOS. - Yong-Un Jeong; Joo-Hyung Chae; Sungphil Choi; Jaekwang Yun; Shin-Hyun Jeong; Suhwan Kim 001 (ISLPED, 2019)

A 10.4-Gb/s 1-Tap Decision Feedback Equalizer With Different Pull-Up and Pull-Down Tap Weights for Asymmetric Memory Interfaces. - Joo-Hyung Chae; Minchang Kim; Sungphil Choi; Suhwan Kim 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

A Differentiating Receiver With a Transition-Detecting DFE for Dual-Rank Mobile Memory Interface. - Sungphil Choi; Yong-Un Jeong; Joo-Hyung Chae; Shin-Hyun Jeong; Suhwan Kim 001 (IEEE Access, 2021)

A 10 Gb/s/pin Single-Ended Transmitter With Reflection-Aided Duobinary Modulation for Dual-Rank Mobile Memory Interfaces. - Yong-Un Jeong; Sungphil Choi; Joo-Hyung Chae; Jaekwang Yun; Shin-Hyun Jeong; Suhwan Kim 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

Single-Ended Receiver-Side Crosstalk Cancellation With Independent Gain and Timing Control for Minimum Residual FEXT. - Yong-Un Jeong; Sungphil Choi; Suhwan Kim 001; Joo-Hyung Chae (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

13.8 A 1a-nm 1.05V 10.5Gb/s/pin 16Gb LPDDR5 Turbo DRAM with WCK Correction Strategy, a Voltage-Offset-Calibrated Receiver and Parasitic Capacitance Reduction. - Yangho Seo; Jihee Choi; Sunki Cho; Hyunwook Han; Wonjong Kim; Gyeongha Ryu; Jungil Ahn; Younga Cho; Sungphil Choi; Seohee Lee; Wooju Lee; Chaehyuk Lee; et al. (ISSCC, 2024)