A task-level pipelined many-SIMD augmented reality processor with congestion-aware network-on-chip scheduler. - Gyeonghoon Kim; Seongwook Park; Kyuho Lee 001; Youchang Kim; Injoon Hong; Kyeongryeol Bong; Dongjoo Shin; Sungpill Choi; Junyoung Park 002; Hoi-Jun Yoo (COOL Chips, 2014)

10.4 A 1.22TOPS and 1.52mW/MHz augmented reality multi-core processor with neural network NoC for HMD applications. - Gyeonghoon Kim; Youchang Kim; Kyuho Lee 001; Seongwook Park; Injoon Hong; Kyeongryeol Bong; Dongjoo Shin; Sungpill Choi; Jinwook Oh; Hoi-Jun Yoo (ISSCC, 2014)

K-glass: Real-time markerless augmented reality smart glasses platform. - Gyeonghoon Kim; Sungpill Choi; Hoi-Jun Yoo (ICIT, 2015)

A 124.9fps memory-efficient hand segmentation processor for hand gesture in mobile devices. - Sungpill Choi; Seongwook Park; Gyeonghoon Kim; Hoi-Jun Yoo (ISCAS, 2015)

4.6 A1.93TOPS/W scalable deep learning/inference processor with tetra-parallel MIMD architecture for big-data applications. - Seongwook Park; Kyeongryeol Bong; Dongjoo Shin; Jinmook Lee; Sungpill Choi; Hoi-Jun Yoo (ISSCC, 2015)

An Energy-Efficient and Scalable Deep Learning/Inference Processor With Tetra-Parallel MIMD Architecture for Big Data Applications. - Seongwook Park; Junyoung Park 002; Kyeongryeol Bong; Dongjoo Shin; Jinmook Lee; Sungpill Choi; Hoi-Jun Yoo (IEEE Trans. Biomed. Circuits Syst., 2015)

A 34pJ/level pixel depth-estimation processor with shifter-based pipelined architecture for mobile user interface. - Sungpill Choi; Seongwook Park; Hoi-Jun Yoo (A-SSCC, 2016)

A 43.7 mW 94 fps CMOS image sensor-based stereo matching accelerator with focal-plane rectification and analog census transformation. - Changhyeon Kim; Kyeongryeol Bong; Sungpill Choi; Hoi-Jun Yoo (ISCAS, 2016)

14.1 A 126.1mW real-time natural UI/UX processor with embedded deep-learning core for low-power smart glasses. - Seongwook Park; Sungpill Choi; Jinmook Lee; Minseo Kim; Junyoung Park 002; Hoi-Jun Yoo (ISSCC, 2016)

A CMOS Image Sensor-Based Stereo Matching Accelerator With Focal-Plane Sparse Rectification and Analog Census Transform. - Changhyeon Kim; Kyeongryeol Bong; Sungpill Choi; Kyuho Jason Lee; Hoi-Jun Yoo (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

An ultra-low-power and mixed-mode event-driven face detection SoC for always-on mobile applications. - Changhyeon Kim; Kyeongryeol Bong; Injoon Hong; Kyuho Lee 001; Sungpill Choi; Hoi-Jun Yoo (ESSCIRC, 2017)

14.6 A 0.62mW ultra-low-power convolutional-neural-network face-recognition processor and a CIS integrated with always-on haar-like face detector. - Kyeongryeol Bong; Sungpill Choi; Changhyeon Kim; Sanghoon Kang; Youchang Kim; Hoi-Jun Yoo (ISSCC, 2017)

Low-Power Convolutional Neural Network Processor for a Face-Recognition System. - Kyeongryeol Bong; Sungpill Choi; Changhyeon Kim; Hoi-Jun Yoo (IEEE Micro, 2017)

A 141.4 mW Low-Power Online Deep Neural Network Training Processor for Real-time Object Tracking in Mobile Devices. - Donghyeon Han; Jinsu Lee; Jinmook Lee; Sungpill Choi; Hoi-Jun Yoo (ISCAS, 2018)

A 46.1 fps Global Matching Optical Flow Estimation Processor for Action Recognition in Mobile Devices. - Juhyoung Lee; Changhyeon Kim; Sungpill Choi; Dongjoo Shin; Sanghoon Kang; Hoi-Jun Yoo (ISCAS, 2018)

A 9.02mW CNN-stereo-based real-time 3D hand-gesture recognition processor for smart mobile devices. - Sungpill Choi; Jinsu Lee; Kyuho Lee 001; Hoi-Jun Yoo (ISSCC, 2018)

A Low-Power Convolutional Neural Network Face Recognition Processor and a CIS Integrated With Always-on Face Detector. - Kyeongryeol Bong; Sungpill Choi; Changhyeon Kim; Donghyeon Han; Hoi-Jun Yoo (IEEE J. Solid State Circuits, 2018)

CNNP-v2: An Energy Efficient Memory-Centric Convolutional Neural Network Processor Architecture. - Sungpill Choi; Kyeongryeol Bong; Donghyeon Han; Hoi-Jun Yoo (AICAS, 2019)

DT-CNN: Dilated and Transposed Convolution Neural Network Accelerator for Real-Time Image Segmentation on Mobile Devices. - Dongseok Im; Donghyeon Han; Sungpill Choi; Sanghoon Kang; Hoi-Jun Yoo (ISCAS, 2019)

A 2.1TFLOPS/W Mobile Deep RL Accelerator with Transposable PE Array and Experience Compression. - Changhyeon Kim; Sanghoon Kang; Dongjoo Shin; Sungpill Choi; Youngwoo Kim; Hoi-Jun Yoo (ISSCC, 2019)

CNNP-v2: A Memory-Centric Architecture for Low-Power CNN Processor on Domain-Specific Mobile Devices. - Sungpill Choi; Kyeongryeol Bong; Donghyeon Han; Hoi-Jun Yoo (IEEE J. Emerg. Sel. Topics Circuits Syst., 2019)

A 4.45 ms Low-Latency 3D Point-Cloud-Based Neural Network Processor for Hand Pose Estimation in Immersive Wearable Devices. - Dongseok Im; Sanghoon Kang; Donghyeon Han; Sungpill Choi; Hoi-Jun Yoo (VLSI Circuits, 2020)

A 0.5V, 6.2μW, 0.059mm2 Sinusoidal Current Generator IC with 0.088% THD for Bio-Impedance Sensing. - Kwantae Kim; Changhyeon Kim; Sungpill Choi; Hoi-Jun Yoo (VLSI Circuits, 2020)

DT-CNN: An Energy-Efficient Dilated and Transposed Convolutional Neural Network Processor for Region of Interest Based Image Segmentation. - Dongseok Im; Donghyeon Han; Sungpill Choi; Sanghoon Kang; Hoi-Jun Yoo (IEEE Trans. Circuits Syst., 2020)

The Development of Silicon for AI: Different Design Approaches. - Kyuho Jason Lee; Jinmook Lee; Sungpill Choi; Hoi-Jun Yoo (IEEE Trans. Circuits Syst., 2020)

2.4 ATOMUS: A 5nm 32TFLOPS/128TOPS ML System-on-Chip for Latency Critical Applications. - Chang-Hyo Yu; Hyo-Eun Kim; Sungho Shin; Kyeongryeol Bong; Hyunsuk Kim; Yoonho Boo; Jaewan Bae; Minjae Kwon; Karim Charfi; Jinseok Kim 006; Hongyun Kim; Myeongbo Shim; et al. (ISSCC, 2024)