Bit Parallel 6T SRAM In-memory Computing with Reconfigurable Bit-Precision. - Kyeongho Lee; Jinho Jeong 002; Sungsoo Cheon; Woong Choi; Jongsun Park 001 (DAC, 2020)

A Bit-Line Boosting Technique for Fast Bit-Line Computation without Read Disturbance. - Sungsoo Cheon; Jongsun Park 001 (ISOCC, 2020)

A Charge-Sharing based 8T SRAM In-Memory Computing for Edge DNN Acceleration. - Kyeongho Lee; Sungsoo Cheon; Joongho Jo; Woong Choi; Jongsun Park 001 (DAC, 2021)

A 2941-TOPS/W Charge-Domain 10T SRAM Compute-in-Memory for Ternary Neural Network. - Sungsoo Cheon; Kyeongho Lee; Jongsun Park 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)