Correlation Aware Random Pattern Generation for Test Time and Shift Power Reduction of Logic BIST. - Jongho Park; Sangjun Lee; Inhwan Lee; Sungwhan Park; Sungho Kang 001 (ISOCC, 2022)

A New Flip-flop Shared Architecture of Test Point Insertion for Scan Design. - Hyemin Kim; Sangjun Lee; Jongho Park; Sungwhan Park; Sungho Kang 001 (ISOCC, 2023)

A New Zero-Overhead Test Method for Low-Power AI Accelerators. - Sangjun Lee; Jongho Park; Sungwhan Park; Hyemin Kim; Sungho Kang 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2024)