A Four-Channel 32-Gb/s Transceiver With Current-Recycling Output Driver and On-Chip AC Coupling in 65-nm CMOS Process. - Taeho Kim; Sungchun Jang; Sungwoo Kim 001; Sang-Hyeok Chu; Jiheon Park; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

A 20 Gb/s 0.4 pJ/b energy-efficient transmitter driver architecture utilizing constant Gm. - Gyu-Seob Jeong; Sang-Hyeok Chu; Yoonsoo Kim; Sungchun Jang; Sungwoo Kim 001; Woo-Rham Bae; Sung-Yong Cho; Haram Ju; Deog-Kyoon Jeong (A-SSCC, 2015)

A 5-GHz subharmonically injection-locked all-digital PLL with complementary switched injection. - Sung-Yong Cho; Sungwoo Kim 001; Min-Seong Choo; Jinhyung Lee; Han-Gon Ko; Sungchun Jang; Sang-Hyeok Chu; Woo-Rham Bae; Yoonsoo Kim; Deog-Kyoon Jeong (ESSCIRC, 2015)

A compact 22-Gb/s transmitter for optical links with all-digital phase-locked loop. - Sungwoo Kim 001; Sungchun Jang; Jun-Eun Park; Yoonsoo Kim; Gyungock Kim; Deog-Kyoon Jeong (ISCAS, 2015)

20-Gb/s 3.6-VPP-swing source-series-terminated driver with 2-Tap FFE in 65-nm CMOS. - Jun-Eun Park; Yoonsoo Kim; Sungwoo Kim 001; Gyungock Kim; Deog-Kyoon Jeong (ISCAS, 2015)

An all-digital bang-bang PLL using two-point modulation and background gain calibration for spread spectrum clock generation. - Sungchun Jang; Sungwoo Kim 001; Sang-Hyeok Chu; Gyu-Seob Jeong; Yoonsoo Kim; Deog-Kyoon Jeong (VLSIC, 2015)

A 22 to 26.5 Gb/s Optical Receiver With All-Digital Clock and Data Recovery in a 65 nm CMOS Process. - Sang-Hyeok Chu; Woo-Rham Bae; Gyu-Seob Jeong; Sungchun Jang; Sungwoo Kim 001; Jiho Joo; Gyungock Kim; Deog-Kyoon Jeong (IEEE J. Solid State Circuits, 2015)

An Optimum Loop Gain Tracking All-Digital PLL Using Autocorrelation of Bang-Bang Phase-Frequency Detection. - Sungchun Jang; Sungwoo Kim 001; Sang-Hyeok Chu; Gyu-Seob Jeong; Yoonsoo Kim; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

A theoretical analysis of phase shift in pulse injection-locked oscillators. - Jinhyung Lee; Sungwoo Kim 001; Min-Seong Choo; Sung-Yong Cho; Han-Gon Ko; Deog-Kyoon Jeong (ISCAS, 2016)

A 20 Gb/s 0.4 pJ/b Energy-Efficient Transmitter Driver Utilizing Constant- Gm Bias. - Gyu-Seob Jeong; Sang-Hyeok Chu; Yoonsoo Kim; Sungchun Jang; Sungwoo Kim 001; Woo-Rham Bae; Sung-Yong Cho; Haram Ju; Deog-Kyoon Jeong (IEEE J. Solid State Circuits, 2016)

29.7 A 2.5GHz injection-locked ADPLL with 197fsrms integrated jitter and -65dBc reference spur using time-division dual calibration. - Sungwoo Kim 001; Han-Gon Ko; Sung-Yong Cho; Jinhyung Lee; Soyeong Shin; Min-Seong Choo; Hankyu Chi; Deog-Kyoon Jeong (ISSCC, 2017)

A 55.1 mW 1.62-to-8.1 Gb/s Video Interface Receiver Generating up to 680 MHz Stream Clock Over 20 dB Loss Channel. - Kwanseo Park; Jinhyung Lee; Kwangho Lee; Min-Seong Choo; Sungchun Jang; Sang-Hyeok Chu; Sungwoo Kim 001; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

A 2.5-5.6 GHz Subharmonically Injection-Locked All-Digital PLL With Dual-Edge Complementary Switched Injection. - Sung-Yong Cho; Sungwoo Kim 001; Min-Seong Choo; Han-Gon Ko; Jinhyung Lee; Woo-Rham Bae; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

56Gb/s PAM-4 VCSEL Transmitter with Quarter-Rate Forwarded Clock using 65nm CMOS Circuits. - Jeongho Hwang; Hyungrok Do; Hong-Seok Choi; Gyu-Seob Jeong; Daehyun Koh; Sungwoo Kim 001; Deog-Kyoon Jeong (OFC, 2019)

A 64Gb/s 2.29pJ/b PAM-4 VCSEL Transmitter With 3-Tap Asymmetric FFE in 65nm CMOS. - Jeongho Hwang; Hong-Seok Choi; Hyungrok Do; Gyu-Seob Jeong; Daehyun Koh; Kwanseo Park; Sungwoo Kim 001; Deog-Kyoon Jeong (VLSI Circuits, 2019)

A PVT Variation-Robust All-Digital Injection-Locked Clock Multiplier With Real-Time Offset Tracking Using Time-Division Dual Calibration. - Min-Seong Choo; Sungwoo Kim 001; Han-Gon Ko; Sung-Yong Cho; Kwanseo Park; Jinhyung Lee; Soyeong Shin; Hankyu Chi; Deog-Kyoon Jeong (IEEE J. Solid State Circuits, 2021)

A Low-Jitter 8-GHz RO-Based ADPLL With PVT-Robust Replica-Based Analog Closed Loop for Supply Noise Compensation. - Hyojun Kim; Woosong Jung; Kwandong Kim; Sungwoo Kim 001; Woo-Seok Choi; Deog-Kyoon Jeong (IEEE J. Solid State Circuits, 2022)

A 2.5-32 Gb/s Gen 5-PCIe Receiver With Multi-Rate CDR Engine and Hybrid DFE. - Moon-Chul Choi; Sanghee Lee 002; Seungha Roh; Kwangho Lee; Jonghyun Oh; Sungwoo Kim 001; Kwandong Kim; Woo-Seok Choi; Jaeha Kim; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. II Express Briefs, 2022)