Simultaneous peak and average power minimization during datapath scheduling for DSP processors. - Saraju P. Mohanty; N. Ranganathan; Sunil K. Chappidi (ACM Great Lakes Symposium on VLSI, 2003)

Power Fluctuation Minimization During Behavioral Synthesis using ILP-Based Datapath Scheduling. - Saraju P. Mohanty; N. Ranganathan; Sunil K. Chappidi (ICCD, 2003)

Transient power minimization through datapath scheduling in multiple supply voltage environment. - Saraju P. Mohanty; Nagarajan Ranganathan; Sunil K. Chappidi (ICECS, 2003)

An ILP-based scheduling scheme for energy efficient high performance datapath synthesis. - Saraju P. Mohanty; N. Ranganathan; Sunil K. Chappidi (ISCAS (5), 2003)

Peak Power Minimization Through Datapath Scheduling. - Saraju P. Mohanty; N. Ranganathan; Sunil K. Chappidi (ISVLSI, 2003)

ILP Models for Energy and Transient Power Minimization During Behavioral Synthesis. - Saraju P. Mohanty; Nagarajan Ranganathan; Sunil K. Chappidi (VLSI Design, 2004)

ILP models for simultaneous energy and transient power minimization during behavioral synthesis. - Saraju P. Mohanty; N. Ranganathan; Sunil K. Chappidi (ACM Trans. Design Autom. Electr. Syst., 2006)