Test generation for MOS circuits using D-algorithm. - Sunil K. Jain; Vishwani D. Agrawal (DAC, 1983)

Test strategy for microprocessers. - Sunil K. Jain; Alfred K. Susskind (DAC, 1983)

STAFAN: An alternative to fault simulation. - Sunil K. Jain; Vishwani D. Agrawal (DAC, 1984)

A gate level model for CMOS combinational logic circuits with application to fault detection. - Sudhakar M. Reddy; Vishwani D. Agrawal; Sunil K. Jain (DAC, 1984)

Statistical Fault Analysis. - Sunil K. Jain; Vishwani D. Agrawal (IEEE Des. Test, 1985)

Modeling and Test Generation Algorithms for MOS Circuits. - Sunil K. Jain; Vishwani D. Agrawal (IEEE Trans. Computers, 1985)

Built-in Self Testing of Embedded Memories. - Sunil K. Jain; Charles E. Stroud (IEEE Des. Test, 1986)

Testing beyond EPA: TDF methodology solutions matrix. - Sunil K. Jain; Greg P. Chema (ITC, 2001)