An Efficient RF Energy Harvester with Tuned Matching Circuit. - Sachin Agrawal; Sunil Kumar Pandey; Jawar Singh; Pravin Neminath Kondekar (VDAT, 2013)

Realization of efficient RF energy harvesting circuits employing different matching technique. - Sachin Agrawal; Sunil Kumar Pandey; Jawar Singh; Manoj Singh Parihar (ISQED, 2014)

A low power and high gain CMOS LNA for UWB applications in 90 nm CMOS process. - Sunil Kumar Pandey; Jawar Singh (Microelectron. J., 2015)

A 0.9V, 3.1-10.6 GHz CMOS LNA with high gain and wideband input match in 90 nm CMOS process. - Sunil Kumar Pandey; Pravin Neminath Kondekar; Kaushal Nigam; Dheeraj Sharma (APCCAS, 2016)

A 45-fsrms Accumulated Jitter PLL Using Advanced Design Techniques for PCIe Gen6 Reference Clock Generation in 2 nm MBCFET Technology. - Subhadeep Datta; Arnab Banerjee; Ayush Tripathi; Dongmin Kang; Leesunghyuck; Hasung Lim; Wonsik Yu; Kgj Vishnu; Chanyoung Jeong; Sumanth Chakkirala; Avneesh Singh Verma; Sachin Kashyap; et al. (A-SSCC, 2024)