VIS: A System for Verification and Synthesis. - Robert K. Brayton; Gary D. Hachtel; Alberto L. Sangiovanni-Vincentelli; Fabio Somenzi; Adnan Aziz; Szu-Tsung Cheng; Stephen A. Edwards; Sunil P. Khatri; Yuji Kukimoto; Abelardo Pardo; Shaz Qadeer; Rajeev K. Ranjan 001; et al. (CAV, 1996)

Engineering Change in a Non-Deterministic FSM Setting. - Sunil P. Khatri; Amit Narayan; Sriram C. Krishnan; Kenneth L. McMillan; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (DAC, 1996)

VIS. - Robert K. Brayton; Gary D. Hachtel; Alberto L. Sangiovanni-Vincentelli; Fabio Somenzi; Adnan Aziz; Szu-Tsung Cheng; Stephen A. Edwards; Sunil P. Khatri; Yuji Kukimoto; Abelardo Pardo; Shaz Qadeer; Rajeev K. Ranjan 001; et al. (FMCAD, 1996)

Decomposition Techniques for Efficient ROBDD Construction. - Jawahar Jain; Amit Narayan; C. Coelho 001; Sunil P. Khatri; Alberto L. Sangiovanni-Vincentelli; Robert K. Brayton; Masahiro Fujita (FMCAD, 1996)

A study of composition schemes for mixed apply/compose based construction of ROBDDs. - Amit Narayan; Sunil P. Khatri; Jawahar Jain; Masahiro Fujita; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (VLSI Design, 1996)

A Novel VLSI Layout Fabric for Deep Sub-Micron Applications. - Sunil P. Khatri; Amit Mehrotra; Robert K. Brayton; Ralph H. J. M. Otten; Alberto L. Sangiovanni-Vincentelli (DAC, 1999)

Multi-Valued Logic Synthesis. - Robert K. Brayton; Sunil P. Khatri (VLSI Design, 1999)

Sequential Multi-Valued Network Simplification using Redundancy Removal. - Sunil P. Khatri; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (VLSI Design, 1999)

Cross-Talk Immune VLSI Design Using a Network of PLAs Embedded in a Regular Layout Fabric. - Sunil P. Khatri; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (ICCAD, 2000)

Binary and Multi-Valued SPFD-Based Wire Removal in PLA Networks. - Subarnarekha Sinha; Sunil P. Khatri; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (ICCD, 2000)

Analysis and avoidance of cross-talk in on-chip buses. - Chunjie Duan; Anup Tirumala; Sunil P. Khatri (Hot Interconnects, 2001)

Addressing the Timing Closure Problem by Integrating Logic Optimization and Placement. - Wilsin Gosti; Sunil P. Khatri; Alberto L. Sangiovanni-Vincentelli (ICCAD, 2001)

A regularity-driven fast gridless detailed router for high frequency datapath designs. - Sabyasachi Das; Sunil P. Khatri (ISPD, 2001)

An efficient and regular routing methodology for datapath designsusing net regularity extraction. - Sabyasachi Das; Sunil P. Khatri (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

A fast ternary CAM design for IP networking applications. - Bruce Gamache; Zachary Pfeffer; Sunil P. Khatri (ICCCN, 2003)

IP routing table compression using ESPRESSO-MV. - Jianjian Bian; Sunil P. Khatri (ICON, 2003)

An ASIC design methodology with predictably low leakage, using leakage-immune standard cells. - Nikhil Jayakumar; Sunil P. Khatri (ISLPED, 2003)

A robust algorithm for approximate compatible observability don't care (CODC) computation. - Nikhil Saluja; Sunil P. Khatri (DAC, 2004)

Exploiting Crosstalk to Speed up On-Chip Buse. - Chunjie Duan; Sunil P. Khatri (DATE, 2004)

High-throughput VLSI implementations of iterative decoders and related code construction problems. - Vijay Nagarajan; Nikhil Jayakumar; Sunil P. Khatri; Olgica Milenkovic (GLOBECOM, 2004)

A metal and via maskset programmable VLSI design methodology using PLAs. - Nikhil Jayakumar; Sunil P. Khatri (ICCAD, 2004)

A novel clock distribution and dynamic de-skewing methodology. - Arjun Kapoor; Nikhil Jayakumar; Sunil P. Khatri (ICCAD, 2004)

SPFD-based wire removal in standard-cell and network-of-PLA circuits. - Sunil P. Khatri; Subarnarekha Sinha; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

A dynamic voltage scaling algorithm for energy reduction in hard real-time systems. - Van R. Culver; Sunil P. Khatri (ASP-DAC, 2005)

A self-adjusting scheme to determine the optimum RBB by monitoring leakage currents. - Nikhil Jayakumar; Sandeep Dhar; Sunil P. Khatri (DAC, 2005)

A variation tolerant subthreshold design approach. - Nikhil Jayakumar; Sunil P. Khatri (DAC, 2005)

Encoding-Based Minimization of Inductive Cross-Talk for Off-Chip Data Transmission. - Brock J. LaMeres; Sunil P. Khatri (DATE, 2005)

A Boolean satisfiability based solution to the routing and wavelength assignment problem in optical telecommunication networks. - John Valavi; Nikhil Saluja; Sunil P. Khatri (ICC, 2005)

Practical techniques to reduce skew and its variations in buffered clock networks. - Ganesh Venkataraman; Nikhil Jayakumar; Jiang Hu; Peng Li 001; Sunil P. Khatri; Anand Rajaram; Patrick McGuinness; Charles J. Alpert (ICCAD, 2005)

X-Routing using Two Manhattan Route Instances. - Seraj Ahmad; Nikhil Jayakumar; Vijay Balasubramanian; Edward Hursey; Sunil P. Khatri; Rabi N. Mahapatra (ICCD, 2005)

Minimum Energy Near-threshold Network of PLA based Design. - Nikhil Jayakumar; Sunil P. Khatri (ICCD, 2005)

Broadband Impedance Matching for Inductive Interconnect in VLSI Packages. - Brock J. LaMeres; Sunil P. Khatri (ICCD, 2005)

Performance model for inter-chip communication considering inductive cross-talk and cost. - Brock J. LaMeres; Sunil P. Khatri (ISCAS (4), 2005)

An algebraic decision diagram (ADD) based technique to find leakage histograms of combinational designs. - Kanupriya Gulati; Nikhil Jayakumar; Sunil P. Khatri (ISLPED, 2005)

Efficient SAT-based combinational ATPG using multi-level don't-cares. - Nikhil Saluja; Sunil P. Khatri (ITC, 2005)

Non-Manhattan Routing Using a Manhattan Router. - Edward Hursey; Nikhil Jayakumar; Sunil P. Khatri (VLSI Design, 2005)

Controlling inductive cross-talk and power in off-chip buses using CODECs. - Brock J. LaMeres; Kanupriya Gulati; Sunil P. Khatri (ASP-DAC, 2006)

A design approach for radiation-hard digital electronics. - Rajesh Garg; Nikhil Jayakumar; Sunil P. Khatri; Gwan Choi (DAC, 2006)

A PLA based asynchronous micropipelining approach for subthreshold circuit design. - Nikhil Jayakumar; Rajesh Garg; Bruce Gamache; Sunil P. Khatri (DAC, 2006)

Bus stuttering: an encoding technique to reduce inductive noise in off-chip data transmission. - Brock J. LaMeres; Sunil P. Khatri (DATE, 2006)

Resource and delay efficient matrix multiplication using newer FPGA devices. - Scott J. Campbell; Sunil P. Khatri (ACM Great Lakes Symposium on VLSI, 2006)

A design flow to optimize circuit delay by using standard cells and PLAs. - Rajesh Garg; Mario Sánchez; Kanupriya Gulati; Nikhil Jayakumar; Anshul Gupta; Sunil P. Khatri (ACM Great Lakes Symposium on VLSI, 2006)

Implementation of MOSFET based capacitors for digital applications. - Bo Shen; Sunil P. Khatri; Takis Zourntos (ACM Great Lakes Symposium on VLSI, 2006)

A High-Speed Fully-Programmable VLSI Decoder for Regular LDPC Codes. - Euncheol Kim; Nikhil Jayakumar; Pankaj Bhagawat; Anand Selvarathinam; Gwan Choi; Sunil P. Khatri (ICASSP (3), 2006)

Network coding for routability improvement in VLSI. - Nikhil Jayakumar; Sunil P. Khatri; Kanupriya Gulati; Alexander Sprintson (ICCAD, 2006)

On the Improvement of Statistical Static Timing Analysis. - Rajesh Garg; Nikhil Jayakumar; Sunil P. Khatri (ICCD, 2006)

CMOS Comparators for High-Speed and Low-Power Applications. - Eric Menendez; Dumezie Maduike; Rajesh Garg; Sunil P. Khatri (ICCD, 2006)

An Efficient, Scalable Hardware Engine for Boolean SATisfiability. - Mandar Waghmode; Kanupriya Gulati; Sunil P. Khatri; Weiping Shi (ICCD, 2006)

Memory-based crosstalk canceling CODECs for on-chip buses. - Chunjie Duan; Kanupriya Gulati; Sunil P. Khatri (ISCAS, 2006)

Computing during supply voltage switching in DVS enabled real-time processors. - Chunjie Duan; Sunil P. Khatri (ISCAS, 2006)

Generalized buffering of PTL logic stages using Boolean division. - Rajesh Garg; Sunil P. Khatri (ISCAS, 2006)

A probabilistic method to determine the minimum leakage vector for combinational designs. - Kanupriya Gulati; Nikhil Jayakumar; Sunil P. Khatri (ISCAS, 2006)

Efficient don't care computation for hierarchical designs. - Kanupriya Gulati; M. Lovell; Sunil P. Khatri (ISCAS, 2006)

An algorithm to minimize leakage through simultaneous input vector control and circuit modification. - Nikhil Jayakumar; Sunil P. Khatri (DATE, 2007)

Toggle Equivalence Preserving (TEP) Logic Optimization. - Eugene Goldberg; Kanupriya Gulati; Sunil P. Khatri (DSD, 2007)

A Structured ASIC Design Approach Using Pass Transistor Logic. - Kanupriya Gulati; Nikhil Jayakumar; Sunil P. Khatri (ISCAS, 2007)

A methodology for interconnect dimension determination. - Jeff L. Cobb; Rajesh Garg; Sunil P. Khatri (ISPD, 2007)

A Predictably Low-Leakage ASIC Design Style. - Nikhil Jayakumar; Sunil P. Khatri (IEEE Trans. Very Large Scale Integr. Syst., 2007)

High-throughput VLSI Implementations of Iterative Decoders and Related Code Construction Problems. - Vijay Nagarajan; Stefan Laendner; Nikhil Jayakumar; Olgica Milenkovic; Sunil P. Khatri (J. VLSI Signal Process., 2007)

Forbidden transition free crosstalk avoidance CODEC design. - Chunjie Duan; Chengyu Zhu; Sunil P. Khatri (DAC, 2008)

A fast, analytical estimator for the SEU-induced pulse width in combinational designs. - Rajesh Garg; Charu Nagpal; Sunil P. Khatri (DAC, 2008)

Towards acceleration of fault simulation using graphics processing units. - Kanupriya Gulati; Sunil P. Khatri (DAC, 2008)

Clock Distribution Scheme using Coplanar Transmission Lines. - Victor H. Cordero Calle; Sunil P. Khatri (DATE, 2008)

Energy Efficient and High Speed On-Chip Ternary Bus. - Chunjie Duan; Sunil P. Khatri (DATE, 2008)

A Single-supply True Voltage Level Shifter. - Rajesh Garg; Gagandeep Mallarapu; Sunil P. Khatri (DATE, 2008)

A Delay-efficient Radiation-hard Digital Design Approach Using CWSP Elements. - Charu Nagpal; Rajesh Garg; Sunil P. Khatri (DATE, 2008)

A lithography-friendly structured ASIC design approach. - Salman Gopalani; Rajesh Garg; Sunil P. Khatri; Mosong Cheng (ACM Great Lakes Symposium on VLSI, 2008)

Improving FPGA routability using network coding. - Kanupriya Gulati; Sunil P. Khatri (ACM Great Lakes Symposium on VLSI, 2008)

Pipelined network of PLA based circuit design. - Suganth Paul; Rajesh Garg; Sunil P. Khatri (ACM Great Lakes Symposium on VLSI, 2008)

A robust, fast pulsed flip-flop design. - Arunprasad Venkatraman; Rajesh Garg; Sunil P. Khatri (ACM Great Lakes Symposium on VLSI, 2008)

A novel, highly SEU tolerant digital circuit design approach. - Rajesh Garg; Sunil P. Khatri (ICCD, 2008)

Modeling dynamic stability of SRAMS in the presence of single event upsets (SEUs). - Rajesh Garg; Peng Li 001; Sunil P. Khatri (ISCAS, 2008)

A Merged Synthesis Technique for Fast Arithmetic Blocks Involving Sum-of-Products and Shifters. - Sabyasachi Das; Sunil P. Khatri (VLSI Design, 2008)

A Timing-Driven Synthesis Technique for Arithmetic Product-of-Sum Expressions. - Sabyasachi Das; Sunil P. Khatri (VLSI Design, 2008)

An Inversion-Based Synthesis Approach for Area and Power Efficient Arithmetic Sum-of-Products. - Sabyasachi Das; Sunil P. Khatri (VLSI Design, 2008)

Efficient, scalable hardware engine for Boolean satisfiability and unsatisfiable core extraction. - Kanupriya Gulati; Mandar Waghmode; Sunil P. Khatri; Weiping Shi (IET Comput. Digit. Tech., 2008)

A probabilistic method to determine the minimum leakage vector for combinational designs in the presence of random PVT variations. - Kanupriya Gulati; Nikhil Jayakumar; Sunil P. Khatri; D. M. H. Walker (Integr., 2008)

A Timing-Driven Approach to Synthesize Fast Barrel Shifters. - Sabyasachi Das; Sunil P. Khatri (IEEE Trans. Circuits Syst. II Express Briefs, 2008)

Resource sharing among mutually exclusive sum-of-product blocks for area reduction. - Sabyasachi Das; Sunil P. Khatri (ACM Trans. Design Autom. Electr. Syst., 2008)

SAT-based ATPG using multilevel compatible don't-cares. - Nikhil Saluja; Kanupriya Gulati; Sunil P. Khatri (ACM Trans. Design Autom. Electr. Syst., 2008)

A Novel Hybrid Parallel-Prefix Adder Architecture With Efficient Timing-Area Characteristic. - Sabyasachi Das; Sunil P. Khatri (IEEE Trans. Very Large Scale Integr. Syst., 2008)

Dynamically De-Skewable Clock Distribution Methodology. - Arjun Kapoor; Nikhil Jayakumar; Sunil P. Khatri (IEEE Trans. Very Large Scale Integr. Syst., 2008)

Highly parallel decoding of space-time codes on graphics processing units. - Kalyana C. Bollapalli; Yiyue Wu; Kanupriya Gulati; Sunil P. Khatri; A. Robert Calderbank (Allerton, 2009)

Efficient analytical determination of the SEU-induced pulse shape. - Rajesh Garg; Sunil P. Khatri (ASP-DAC, 2009)

Fast circuit simulation on graphics processing units. - Kanupriya Gulati; John F. Croix; Sunil P. Khatri; Rahm Shastry (ASP-DAC, 2009)

Accelerating statistical static timing analysis using graphics processing units. - Kanupriya Gulati; Sunil P. Khatri (ASP-DAC, 2009)

Closed-loop modeling of power and temperature profiles of FPGAs. - Kanupriya Gulati; Sunil P. Khatri; Peng Li 001 (FPGA, 2009)

Low power and high performance sram design using bank-based selective forward body bias. - Kalyana C. Bollapalli; Rajesh Garg; Kanupriya Gulati; Sunil P. Khatri (ACM Great Lakes Symposium on VLSI, 2009)

Robust window-based multi-node technology-independent logic minimization. - Jeff L. Cobb; Kanupriya Gulati; Sunil P. Khatri (ACM Great Lakes Symposium on VLSI, 2009)

Fault table generation using Graphics Processing Units. - Kanupriya Gulati; Sunil P. Khatri (HLDVT, 2009)

Introduction to GPU programming for EDA. - John F. Croix; Sunil P. Khatri (ICCAD, 2009)

On-chip bidirectional wiring for heavily pipelined systems using network coding. - Kalyana C. Bollapalli; Rajesh Garg; Kanupriya Gulati; Sunil P. Khatri (ICCD, 2009)

3D simulation and analysis of the radiation tolerance of voltage scaled digital circuit. - Rajesh Garg; Sunil P. Khatri (ICCD, 2009)

A PLL design based on a standing wave resonant oscillator. - Vinay Karkala; Kalyana C. Bollapalli; Rajesh Garg; Sunil P. Khatri (ICCD, 2009)

A robust pulsed flip-flop and its use in enhanced scan design. - Rajesh Kumar; Kalyana C. Bollapalli; Rajesh Garg; Tarun Soni; Sunil P. Khatri (ICCD, 2009)

A radiation tolerant Phase Locked Loop design for digital electronics. - Rajesh Kumar; Vinay Karkala; Rajesh Garg; Tanuj Jindal; Sunil P. Khatri (ICCD, 2009)

Sorting Binary Numbers in Hardware - A Novel Algorithm and its Implementation. - Srikanth Alaparthi; Kanupriya Gulati; Sunil P. Khatri (ISCAS, 2009)

SEU hardened clock regeneration circuits. - Rajballav Dash; Rajesh Garg; Sunil P. Khatri; Gwan S. Choi (ISQED, 2009)

Design and implementation of a sub-threshold BFSK transmitter. - Suganth Paul; Rajesh Garg; Sunil P. Khatri; Sheila Vaidya (ISQED, 2009)

Noise-Based Logic and Computing: From Boolean Logic Gates to Brain Circuitry and Its Possible Hardware Realization. - Laszlo B. Kish; Sergey M. Bezrukov; Sunil P. Khatri; Zoltan Gingl; S. Sethuraman (IWNC, 2009)

Selective Forward Body Bias for High Speed and Low Power SRAMs. - Kalyana C. Bollapalli; Rajesh Garg; Kanupriya Gulati; Sunil P. Khatri (J. Low Power Electron., 2009)

Encoding Serial Graphical Data for Energy-Delay Product/Energy Minimization. - Sasidharan Ekambavanan; Rajesh Garg; Sunil P. Khatri; Krishna R. Narayanan (J. Low Power Electron., 2009)

FPGA-based hardware acceleration for Boolean satisfiability. - Kanupriya Gulati; Suganth Paul; Sunil P. Khatri; Srinivas Patil; Abhijit Jas (ACM Trans. Design Autom. Electr. Syst., 2009)

Efficient On-Chip Crosstalk Avoidance CODEC Design. - Chunjie Duan; Victor H. Cordero Calle; Sunil P. Khatri (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Circuit-Level Design Approaches for Radiation-Hard Digital Electronics. - Rajesh Garg; Nikhil Jayakumar; Sunil P. Khatri; Gwan S. Choi (IEEE Trans. Very Large Scale Integr. Syst., 2009)

A Fast Hardware Approach for Approximate, Efficient Logarithm and Antilogarithm Computations. - Suganth Paul; Nikhil Jayakumar; Sunil P. Khatri (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Implementing digital logic with sinusoidal supplies. - Kalyana C. Bollapalli; Sunil P. Khatri; Laszlo B. Kish (DATE, 2010)

A SAT-Based Scheme to Determine Optimal Fix-Free Codes. - Navid Abedini; Sunil P. Khatri; Serap A. Savari (DCC, 2010)

Inference of gene predictor set using Boolean satisfiability. - Pey-Chang Kent Lin; Sunil P. Khatri (GENSiPS, 2010)

Boolean satisfiability on a graphics processor. - Kanupriya Gulati; Sunil P. Khatri (ACM Great Lakes Symposium on VLSI, 2010)

VLSI implementation of a non-linear feedback shift register for high-speed cryptography applications. - Pey-Chang Kent Lin; Sunil P. Khatri (ACM Great Lakes Symposium on VLSI, 2010)

Efficient arithmetic sum-of-product (SOP) based Multiple Constant Multiplication (MCM) for FFT. - Vinay Karkala; Joseph Wanstrath; Travis Lacour; Sunil P. Khatri (ICCAD, 2010)

An efficient pulse flip-flop based launch-on-shift scan cell. - Rajesh Kumar; Sunil P. Khatri (ISCAS, 2010)

Towards brain-inspired computing - Zoltan Gingl; Sunil P. Khatri; Laszlo B. Kish (CoRR, 2010)

Instantaneous noise-based logic - Laszlo B. Kish; Sunil P. Khatri; Ferdinand Peper (CoRR, 2010)

Computation using Noise-based Logic: Efficient String Verification over a Slow Communication Channel - Laszlo B. Kish; Sunil P. Khatri; Tamás Horváth 001 (CoRR, 2010)

Fault Table Computation on GPUs. - Kanupriya Gulati; Sunil P. Khatri (J. Electron. Test., 2010)

A Simultaneous Input Vector Control and Circuit Modification Technique to Reduce Leakage with Zero Delay Penalty. - Nikhil Jayakumar; Sunil P. Khatri (ACM Trans. Design Autom. Electr. Syst., 2010)

Efficient cancer therapy using Boolean networks and Max-SAT-based ATPG. - Pey-Chang Kent Lin; Sunil P. Khatri (GENSiPS, 2011)

A novel cryptographic key exchange scheme using resistors. - Pey-Chang Kent Lin; Alex Ivanov; Bradley Johnson; Sunil P. Khatri (ICCD, 2011)

An Automated Approach for Minimum Jitter Buffered H-Tree Construction. - Ayan Mandal; Nikhil Jayakumar; Kalyana C. Bollapalli; Sunil P. Khatri; Rabi N. Mahapatra (VLSI Design, 2011)

Interconnected Tile Standing Wave Resonant Oscillator Based Clock Distribution Circuits. - Ayan Mandal; Vinay Karkala; Sunil P. Khatri; Rabi N. Mahapatra (VLSI Design, 2011)

Noise-based information processing: Noise-based logic and computing: what do we have so far? - Laszlo B. Kish; Sunil P. Khatri; Sergey M. Bezrukov; Ferdinand Peper; Zoltan Gingl; Tamás Horváth 001 (CoRR, 2011)

Noise-based Deterministic Logic and Computing: a Brief Survey. - Laszlo B. Kish; Sunil P. Khatri; Sergey M. Bezrukov; Ferdinand Peper; Zoltan Gingl; Tamás Horváth 001 (Int. J. Unconv. Comput., 2011)

A DCVSL Delay Cell for Fast Low Power Frequency Synthesis Applications. - Didem Zeliha Turker; Sunil P. Khatri; Edgar Sánchez-Sinencio (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)

Application of logic synthesis to the understanding and cure of genetic diseases. - Pey-Chang Kent Lin; Sunil P. Khatri (DAC, 2012)

Boolean satisfiability using noise based logic. - Pey-Chang Kent Lin; Ayan Mandal; Sunil P. Khatri (DAC, 2012)

A fast, source-synchronous ring-based network-on-chip design. - Ayan Mandal; Sunil P. Khatri; Rabi N. Mahapatra (DATE, 2012)

Determining gene function in boolean networks using boolean satisfiability. - Pey-Chang Kent Lin; Sunil P. Khatri (GENSiPS, 2012)

Alleviating NBTI-induced failure in off-chip output drivers. - Bhavitavya Bhadviya; Ayan Mandal; Sunil P. Khatri (ACM Great Lakes Symposium on VLSI, 2012)

An efficient arithmetic Sum-of-Product (SOP) based multiplication approach for FIR filters and DFT. - Rajeev Kumar; Ayan Mandal; Sunil P. Khatri (ICCD, 2012)

Architectural simulations of a fast, source-synchronous ring-based Network-on-Chip design. - Ayan Mandal; Sunil P. Khatri; Rabi N. Mahapatra (ICCD, 2012)

Timing aware partitioning for multi-FPGA based logic simulation using top-down selective hierarchy flattening. - Subramanian Poothamkurissi Swaminathan; Pey-Chang Kent Lin; Sunil P. Khatri (ICCD, 2012)

On Optimal and Achievable Fix-Free Codes. - Serap A. Savari; S. M. Hossein Tabatabaei Yazdi; Navid Abedini; Sunil P. Khatri (IEEE Trans. Inf. Theory, 2012)

Crosstalk avoidance codes for 3D VLSI. - Rajeev Kumar; Sunil P. Khatri (DATE, 2013)

Exploring topologies for source-synchronous ring-based network-on-chip. - Ayan Mandal; Sunil P. Khatri; Rabi N. Mahapatra (DATE, 2013)

Mixed structural-functional path delay test generation and compaction. - Kun Bian; D. M. H. Walker; Sunil P. Khatri; Shayak Lahiri (DFTS, 2013)

GPU implementation of a scalable non-linear congruential generator for cryptography applications. - Aditya Belsare; Steve Liu; Sunil P. Khatri (ACM Great Lakes Symposium on VLSI, 2013)

Architecture and 3D device simulation of a PIN diode-based Gamma radiation detector. - Amr Elshennawy; Craig M. Marianno; Sunil P. Khatri (ACM Great Lakes Symposium on VLSI, 2013)

A source-synchronous Htree-based network-on-chip. - Ayan Mandal; Sunil P. Khatri; Rabi N. Mahapatra (ACM Great Lakes Symposium on VLSI, 2013)

Noise-based algorithms for functional equivalence and tautology checking. - Pey-Chang Kent Lin; Sunil P. Khatri (ICCD, 2013)

A low-jitter phase-locked resonant clock generation and distribution scheme. - Ayan Mandal; Kalyana C. Bollapalli; Nikhil Jayakumar; Sunil P. Khatri; Rabi N. Mahapatra (ICCD, 2013)

Using GPUs to Accelerate CAD Algorithms. - John F. Croix; Sunil P. Khatri; Kanupriya Gulati (IEEE Des. Test, 2013)

Look-up Table Design for Deep Sub-threshold through Full-Supply Operation. - Monther Abusultan; Sunil P. Khatri (FCCM, 2014)

FPGA LUT design for wide-band dynamic voltage and frequency scaled operation (abstract only). - Monther Abusultan; Sunil P. Khatri (FPGA, 2014)

A comparison of FinFET based FPGA LUT designs. - Monther Abusultan; Sunil P. Khatri (ACM Great Lakes Symposium on VLSI, 2014)

An asynchronous Network-on-Chip router with low standby power. - Amr Elshennawy; Sunil P. Khatri (ICCD, 2014)

An area-efficient Ternary CAM design using floating gate transistors. - Viacheslav V. Fedorov; Monther Abusultan; Sunil P. Khatri (ICCD, 2014)

Techniques to Improve the Efficiency of SAT Based Path Delay Test Generation. - Kun Bian; D. M. H. Walker; Sunil P. Khatri (VLSID, 2014)

Delay, Power and Energy Tradeoffs in Deep Voltage-scaled FPGAs. - Monther Abusultan; Sunil P. Khatri (ACM Great Lakes Symposium on VLSI, 2015)

An Efficient Approach to Sample On-Chip Power Supplies. - Luke Murray; Sunil P. Khatri (ACM Great Lakes Symposium on VLSI, 2015)

Exploring the viability of stochastic computing. - Joao Marcos de Aguiar; Sunil P. Khatri (ICCD, 2015)

Zero and negative energy dissipation at information-theoretic erasure. - Laszlo B. Kish; Claes-Göran Granqvist; Sunil P. Khatri; Ferdinand Peper (CoRR, 2015)

GPU acceleration for Bayesian control of Markovian genetic regulatory networks. - He Zhou; Jiang Hu; Sunil P. Khatri; Frank Liu 001; Cliff C. N. Sze; Mohammadmahdi R. Yousefi (BHI, 2016)

A practical methodology to validate the statistical behavior of bloom filters. - Venkateshwar Kottapalli; Sunil P. Khatri (CODES+ISSS, 2016)

A GPU-based implementation of a sensor tasking methodology. - Monther Abusultan; Suman Chakravorty; Sunil P. Khatri (FUSION, 2016)

A flash-based digital circuit design flow. - Monther Abusultan; Sunil P. Khatri (ICCAD, 2016)

Implementing low power digital circuits using flash devices. - Monther Abusultan; Sunil P. Khatri (ICCD, 2016)

Exploring static and dynamic flash-based FPGA design topologies. - Monther Abusultan; Sunil P. Khatri (ICCD, 2016)

A novel hardware hash unit design for modern microprocessors. - Abbas A. Fairouz; Monther Abusultan; Sunil P. Khatri (ICCD, 2016)

A Ternary-Valued, Floating Gate Transistor-Based Circuit Design Approach. - Monther Abusultan; Sunil P. Khatri (ISVLSI, 2016)

Response to "Comment on 'Zero and negative energy dissipation at information-theoretic erasure'". - Laszlo B. Kish; Claes-Goran Granqvist; Sunil P. Khatri; Ferdinand Peper (CoRR, 2016)

FTCAM: An Area-Efficient Flash-Based Ternary CAM Design. - Viacheslav V. Fedorov; Monther Abusultan; Sunil P. Khatri (IEEE Trans. Computers, 2016)

Fast and Highly Scalable Bayesian MDP on a GPU Platform. - He Zhou; Sunil P. Khatri; Jiang Hu; Frank Liu 001; Cliff C. N. Sze (BCB, 2017)

Design of a Flash-based Circuit for Multi-valued Logic. - Monther Abusultan; Sunil P. Khatri (ACM Great Lakes Symposium on VLSI, 2017)

Circuit Level Design of a Hardware Hash Unit for use in Modern Microprocessors. - Abbas A. Fairouz; Monther Abusultan; Sunil P. Khatri (ACM Great Lakes Symposium on VLSI, 2017)

A Robust C-element Design with Enhanced Metastability Performance. - Kinshuk Sharma; Sunil P. Khatri (ACM Great Lakes Symposium on VLSI, 2017)

Fast, Ring-Based Design of 3D Stacked DRAM. - Andrew J. Douglass; Sunil P. Khatri (ICCD, 2017)

An FPGA-Based Coprocessor for Hash Unit Acceleration. - Abbas A. Fairouz; Sunil P. Khatri (ICCD, 2017)

A Survey of Software and Hardware Approaches to Performing Read Alignment in Next Generation Sequencing. - Ahmad Al Kawam; Sunil P. Khatri; Aniruddha Datta (IEEE ACM Trans. Comput. Biol. Bioinform., 2017)

A Homomorphic Encryption Scheme Based on Affine Transforms. - Kyle Loyka; He Zhou; Sunil P. Khatri (ACM Great Lakes Symposium on VLSI, 2018)

A Plain-Text Incremental Compression (PIC) Technique with Fast Lookup Ability. - Kunal Bharathi; Harsh Kumar; Abbas A. Fairouz; Ahmad Al Kawam; Sunil P. Khatri (ICCD, 2018)

Synchronization of Ring-Based Resonant Standing Wave Oscillators for 3D Clocking Applications. - Andrew J. Douglass; Sunil P. Khatri (ICCD, 2018)

A GPU-CPU heterogeneous algorithm for NGS read alignment. - Ahmad Al Kawam; Sunil P. Khatri; Aniruddha Datta (Int. J. Comput. Biol. Drug Des., 2018)

Comparing Leakage Reduction Techniques for an Asynchronous Network-on-Chip Router. - Abbas A. Fairouz; Monther Abusultan; Amr Elshennawy; Sunil P. Khatri (J. Low Power Electron., 2018)

A Memory-Efficient Markov Decision Process Computation Framework Using BDD-based Sampling Representation. - He Zhou; Sunil P. Khatri; Jiang Hu; Frank Liu 001 (DAC, 2019)

Threshold Logic in a Flash. - Ankit Wagle; Gian Singh; Jinghua Yang; Sunil P. Khatri; Sarma B. K. Vrudhula (ICCD, 2019)

Fast, Ring-Based Design of 3-D Stacked DRAM. - Andrew J. Douglass; Sunil P. Khatri (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Scaled Population Arithmetic for Efficient Stochastic Computing. - He Zhou; Sunil P. Khatri; Jiang Hu; Frank Liu 001 (ASP-DAC, 2020)

Scaled Population Subtraction for Approximate Computing. - Kunal Bharathi; Jiang Hu; Sunil P. Khatri (ICCD, 2020)

A Configurable BNN ASIC using a Network of Programmable Threshold Logic Standard Cells. - Ankit Wagle; Sunil P. Khatri; Sarma B. K. Vrudhula (ICCD, 2020)

A Mathematical Framework for Exploring Protein Folding Dynamics using Probabilistic Model Checking. - Prasenjit Biswas; Sarit Pal; Sunil P. Khatri (ICICT, 2020)

A Statistical Methodology for Post-Fabrication Weight Tuning in a Binary Perceptron. - Elham Azari; Ankit Wagle; Sunil P. Khatri; Sarma B. K. Vrudhula (ISQED, 2020)

NIST-Lite: Randomness Testing of RNGs on an Energy-Constrained Platform. - Cheng-Yen Lee; Kunal Bharathi; Joellen Lansford; Sunil P. Khatri (ICCD, 2021)

CIDAN: Computing in DRAM with Artificial Neurons. - Gian Singh; Ankit Wagle; Sarma B. K. Vrudhula; Sunil P. Khatri (ICCD, 2021)

Hardware Acceleration of Hash Operations in Modern Microprocessors. - Abbas A. Fairouz; Monther Abusultan; Viacheslav V. Fedorov; Sunil P. Khatri (IEEE Trans. Computers, 2021)

A Flash-based Current-mode IC to Realize Quantized Neural Networks. - Kyler R. Scott; Cheng-Yen Lee; Sunil P. Khatri; Sarma B. K. Vrudhula (DATE, 2022)

TD3lite: FPGA Acceleration of Reinforcement Learning with Structural and Representation Optimizations. - Chan-Wei Hu; Jiang Hu; Sunil P. Khatri (FPL, 2022)

A Flash-based Digital to Analog Converter for Low Power Applications. - Kyler R. Scott; Sunil P. Khatri (ICCD, 2022)

A Novel ASIC Design Flow Using Weight-Tunable Binary Neurons as Standard Cells. - Ankit Wagle; Gian Singh; Sunil P. Khatri; Sarma B. K. Vrudhula (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A Hardware Validation Framework for a Networked Dynamic Multi-factor Security Protocol. - Cheng-Yen Lee; Kyler R. Scott; Sunil P. Khatri; Ali Ghrayeb (CommNet, 2023)

An Extremely Low-voltage Floating Gate Artificial Neuron. - Kyler R. Scott; Sunil P. Khatri (ISCAS, 2023)

Scaled Population Division for Approximate Computing. - Kunal Bharathi; Sunil P. Khatri; Jiang Hu (ISLPED, 2023)

A Novel Pseudo-Flash Based Digital Low Dropout (LDO) Voltage Regulator. - Cheng-Yen Lee; Sunil P. Khatri; Sarma B. K. Vrudhula (ISQED, 2023)

A Digital Low Dropout (LDO) Voltage Regulator Using Pseudoflash Transistors. - Cheng-Yen Lee; Sunil P. Khatri (IEEE Trans. Very Large Scale Integr. Syst., 2023)

Self-Adaptive Physics Informed Neural Network for Paper Insulation Degree of Polymerization Prediction. - Alamera Nouran Alquennah; Mohammad AlShaikh Saleh; Ali Ghrayeb; Haitham Abu-Rub; Shady S. Refaat; Mohammed Abdullah Al-Hajri; Sunil P. Khatri (IECON, 2024)

A Mixed-Signal Quantized Neural Network Accelerator Using Flash Transistors. - Kyler R. Scott; Cheng-Yen Lee; Sunil P. Khatri; Sarma B. K. Vrudhula (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

An ASIC Accelerator for QNN With Variable Precision and Tunable Energy Efficiency. - Ankit Wagle; Gian Singh; Sunil P. Khatri; Sarma B. K. Vrudhula (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

A Novel Mixed-Signal Flash-based Finite Impulse Response (FFIR) Filter for IoT Applications. - Cheng-Yen Lee; Sunil P. Khatri; Ali Ghrayeb (ASP-DAC, 2025)

Classification of Corrosion in Underground Power Cables Using CNNs and Microscopic Imaging. - Alamera Nouran Alquennah; Mohammad AlShaikh Saleh; Shady S. Refaat; Ali Ghrayeb; Haitham Abu-Rub; Marek Olesz; Mohammed Abdullah Al-Hajri; Sunil P. Khatri (EUROCON, 2025)

CapsPDNet: Optimized Capsule Network for Predicting Insulator Discharges Using UHF Signals. - Mohammad AlShaikh Saleh; Ahmad Darwish; Ali Ghrayeb; Shady S. Refaat; Haitham Abu-Rub; Sunil P. Khatri; Ayman H. El-Hag; Celal Fadil Kumru (IEEE Trans. Instrum. Meas., 2025)

Attention-Enhanced AGRU Framework for Induction Motor Incipient Fault Diagnosis in Electric Vehicles. - Mohammad AlShaikh Saleh; Ali Ghrayeb; Shady S. Refaat; Haitham Abu-Rub; Sunil P. Khatri; Jörg Kammermann (IEEE Trans. Instrum. Meas., 2025)