Clause-Column Table Approach for Generating All the Prime Implicants of Switching Functions. - Sunil R. Das; Narinder Singh Khabra (IEEE Trans. Computers, 1972)

Multiform Partial Symmetry and Linearity. - N. S. Khabra; Sunil R. Das (IEEE Trans. Computers, 1973)

Strong connectivity in symmetric graphs and generation of maximal minimally strongly connected subgraphs. - Sunil R. Das; C. L. Sheng (Inf. Sci., 1978)

Transition matrices in the measurement and control of synchronous sequential machines. - Sunil R. Das; C. L. Sheng; Zen Chen; W. J. Hsu (Inf. Sci., 1979)

On random testing of sequential digital logic with a high confidence measure (abstract). - Sunil R. Das (ACM Conference on Computer Science, 1986)

An appraisal of the performance of the MMSC subgraph generation algorithm on a Cyber System 170/720. - Sunil R. Das; S. Y. Lee (Computing, 1986)

Transition submatrices in regular homing experiments and identification of sequential machines of known class using direct-sum transition matrices. - Sunil R. Das; Ping Chao; Zen Chen; Yow Lung Dai; Mrinal K. Das (Comput. Oper. Res., 1987)

A survey on bit dimension optimization strategies of microprograms. - Sunil R. Das; Amiya Nayak (MICRO, 1990)

Multiple-output parity bit signature for exhaustive testing. - Wen-Ben Jone; Sunil R. Das (J. Electron. Test., 1990)

Probabilistic modeling and fault analysis in sequential logic using computer simulation. - Sunil R. Das; Wen-Ben Jone; K. L. Wong (IEEE Trans. Syst. Man Cybern., 1990)

On random testing for combinational circuits with a high measure of confidence. - Sunil R. Das; Wen-Ben Jone (IEEE Trans. Syst. Man Cybern., 1992)

Guest Editorial. - Sunil R. Das (VLSI Design, 1993)

Designing General-Purpose Fault-Tolerant Distributed Systems - A Layered Approach. - Amiya R. Nayak; Wen-Ben Jone; Sunil R. Das (ICPADS, 1994)

On Probabilistic Testing of Large-Scale Sequential Circuits Using Circuit Decomposition. - Sunil R. Das; Wen-Ben Jone; Amiya Nayak; Ian Choi (VLSI Design, 1994)

An improved output compaction technique for built-in self-test in VLSI circuits. - Sunil R. Das; H. T. Ho; Wen-Ben Jone; Amiya R. Nayak (VLSI Design, 1995)

On testing of sequential machines using circuit decomposition and stochastic modeling. - Sunil R. Das; Wen-Ben Jone; Amiya R. Nayak; Ian Choi (IEEE Trans. Syst. Man Cybern., 1995)

CACOP-a random pattern testability analyzer. - Wen-Ben Jone; Sunil R. Das (IEEE Trans. Syst. Man Cybern., 1995)

Syndrome signature in output compaction for VLSI BIST. - Sunil R. Das; Nishith Goel; Wen-Ben Jone; Amiya R. Nayak (VLSI Design, 1996)

PGEN: A Novel Approach to Sequential Circuit Test Generation. - Wen-Ben Jone; Nigam Shah; Anita Gleason; Sunil R. Das (VLSI Design, 1996)

Delay Fault Coverage Enhancement Using Multiple Test Observation Times. - Wen-Ben Jone; Yun-Pan Ho; Sunil R. Das (VLSI Design, 1997)

Delay Fault Coverage Enhancement Using Variable Observation Times. - Wen-Ben Jone; Yun-Pan Ho; Sunil R. Das (J. Electron. Test., 1997)

Pseudorandom encoding for structured light applications. - Emil M. Petriu; Sunil R. Das; Niculaie Trif; Stephen S. K. Yeung (CATA, 1998)

A Stochastic Method for Defect Level Analysis of Pseudorandom Testing. - Wen-Ben Jone; Sunil R. Das (VLSI Design, 1998)

Space compaction under generalized mergeability. - Sunil R. Das; Emil M. Petriu; Tony F. Barakat; Mansour H. Assaf; Amiya R. Nayak (IEEE Trans. Instrum. Meas., 1998)

Syndrome Signature in Output Compaction for VLSI Built-in Self-Test. - Sunil R. Das; Nita Goel; Wen-Ben Jone; Amiya R. Nayak (VLSI Design, 1998)

Test-set embedding based on width compression for mixed-mode BIST. - Krishnendu Chakrabarty; Sunil R. Das (IEEE Trans. Instrum. Meas., 2000)

Space compression revisited. - Sunil R. Das; Tony F. Barakat; Emil M. Petriu; Mansour H. Assaf; Krishnendu Chakrabarty (IEEE Trans. Instrum. Meas., 2000)

An Efficient Parallel Transparent Bist Method For Multiple Embedded Memory Buffers. - Der-Cheng Huang; Wen-Ben Jone; Sunil R. Das (VLSI Design, 2001)

A Parallel Built-In Self-Diagnostic Method For Embedded Memory Buffers. - Der-Cheng Huang; Wen-Ben Jone; Sunil R. Das (VLSI Design, 2001)

Fault tolerance in systems design in VLSI using data compression under constraints of failure probabilities. - Sunil R. Das; Chittoor V. Ramamoorthy; Mansour H. Assaf; Emil M. Petriu; Wen-Ben Jone (IEEE Trans. Instrum. Meas., 2001)

An adaptive path selection method for delay testing. - Wen-Ben Jone; Wu-Sung Yeh; Chingwei Yeh; Sunil R. Das (IEEE Trans. Instrum. Meas., 2001)

Random Pattern Testability Enhancement by Circuit Rewiring. - Shih-Chieh Chang; Kwen-Yo Chen; Ching-Hsiang Cheng; Wen-Ben Jone; Sunil R. Das (VLSI Design, 2001)

Defect Level Estimation for Pseudorandom Testing Using Stochastic Analysis. - Wen-Ben Jone; Der-Cheng Huang; Shih-Chieh Chang; Sunil R. Das (VLSI Design, 2001)

Design of Aliasing Free Space Compressor in BIST with Maximal Compaction Ratio Using Concepts of Strong and Weak Compatibilities of Response Data Outputs and Generalized Sequence Mergeability. - Sunil R. Das; Mansour H. Assaf; Emil M. Petriu; Sujoy Mukherjee (IWDC, 2002)

Data compression in space under generalized mergeability based on concepts of cover table and frequency ordering. - Sunil R. Das; Jing Yi Liang; Emil M. Petriu; Mansour H. Assaf; Wen-Ben Jone; Krishnendu Chakrabarty (IEEE Trans. Instrum. Meas., 2002)

JBits Implementation and Design Verification in Space Compressor Design of Digital Circuits. - Mansour H. Assaf; Rami S. Abielmona; Payam Abolghasem; Sunil R. Das; Emil M. Petriu; Voicu Groza (Modelling, Identification and Control, 2003)

Guest editorial [Special section on innovations in VLSI automatic test equipment (ATEs)]. - Sunil R. Das; Rochit Rajsuman (IEEE Trans. Instrum. Meas., 2003)

Parity bit signature in response data compaction and built-in self-testing of VLSI circuits with nonexhaustive test sets. - Sunil R. Das; Made Sudarma; Mansour H. Assaf; Emil M. Petriu; Wen-Ben Jone; Krishnendu Chakrabarty; Mehmet Sahinoglu (IEEE Trans. Instrum. Meas., 2003)

An efficient BIST method for non-traditional faults of embedded memory arrays. - Wen-Ben Jone; Der-Cheng Huang; Sunil R. Das (IEEE Trans. Instrum. Meas., 2003)

Instrumentation applications of multibit random-data representation. - Emil M. Petriu; Lichen Zhao; Sunil R. Das; Voicu Z. Groza; Aurel Cornell (IEEE Trans. Instrum. Meas., 2003)

Implementation of Embedded Cores-Based Digital Devices in JBits Java Simulation Environment. - Mansour H. Assaf; Rami S. Abielmona; Payam Abolghasem; Sunil R. Das; Emil M. Petriu; Voicu Groza; Mehmet Sahinoglu (CIT, 2004)

Enhancing Testability in Architectural Design for the New Generation of Core-Based Embedded Systems. - Mansour H. Assaf; Sunil R. Das; Emil M. Petriu; Mehmet Sahinoglu (HASE, 2004)

Altera Max Plus II Development Environment in Fault Simulation and Test Implementation of Embedded Cores-Based Sequential Circuits. - Sunil R. Das; Chuan Jin; Liwu Jin; Mansour H. Assaf; Emil M. Petriu; Mehmet Sahinoglu (IWDC, 2004)

Aliasing-Free Compaction in Testing Cores-Based System-on-Chip (SoC) using Compatibility of Response Data outputs. - Sunil R. Das; Mansour H. Assaf; Emil M. Petriu; Mehmet Sahinoglu (Trans. SDPS, 2004)

A parallel built-in self-diagnostic method for nontraditional faults of embedded memory arrays. - Vikram Arora; Wen-Ben Jone; Der-Cheng Huang; Sunil R. Das (IEEE Trans. Instrum. Meas., 2004)

Robotic tactile recognition of pseudorandom encoded objects. - Emil M. Petriu; Stephen K. S. Yeung; Sunil R. Das; Ana-Maria Cretu 001; Hans J. W. Spoelder (IEEE Trans. Instrum. Meas., 2004)

An adaptive compressed MPEG-2 video watermarking scheme. - Satyendra Biswas; Sunil R. Das; Emil M. Petriu (IEEE Trans. Instrum. Meas., 2005)

Getting errors to catch themselves - self-testing of VLSI circuits with built-in hardware. - Sunil R. Das (IEEE Trans. Instrum. Meas., 2005)

Guest Editorial First Special Section of the IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT in the Area of VLSI Testing - Future of Semiconductor Test. - Sunil R. Das; Rochit Rajsuman (IEEE Trans. Instrum. Meas., 2005)

Revisiting response compaction in space for full-scan circuits with nonexhaustive test sets using concept of sequence characterization. - Sunil R. Das; Chittoor V. Ramamoorthy; Mansour H. Assaf; Emil M. Petriu; Wen-Ben Jone; Mehmet Sahinoglu (IEEE Trans. Instrum. Meas., 2005)

Fault simulation and response compaction in full scan circuits using HOPE. - Sunil R. Das; Chittoor V. Ramamoorthy; Mansour H. Assaf; Emil M. Petriu; Wen-Ben Jone; Mehmet Sahinoglu (IEEE Trans. Instrum. Meas., 2005)

A built-in self-testing method for embedded multiport memory arrays. - Vinod Narayanan; Swaroop Ghosh; Wen-Ben Jone; Sunil R. Das (IEEE Trans. Instrum. Meas., 2005)

Measuring availability indexes with small samples for component and network reliability using the Sahinoglu-Libby probability model. - Mehmet Sahinoglu; David L. Libby; Sunil R. Das (IEEE Trans. Instrum. Meas., 2005)

Space compactor design in VLSI circuits based on graph theoretic concepts. - Satyendra Biswas; Sunil R. Das; Emil M. Petriu (IEEE Trans. Instrum. Meas., 2006)

Guest Editorial Second Special Section of the IEEE Transactions on Instrumentation and Measurement in the Area of VLSI Testing - Future of Semiconductor Test. - Sunil R. Das; Rochit Rajsuman (IEEE Trans. Instrum. Meas., 2006)

Crosstalk test pattern generation for dynamic programmable logic arrays. - Jianxun Liu; Wen-Ben Jone; Sunil R. Das (IEEE Trans. Instrum. Meas., 2006)

Testing Analog and Mixed-Signal Circuits With Built-In Hardware - A New Approach. - Sunil R. Das; Jila Zakizadeh; Satyendra Biswas; Mansour H. Assaf; Amiya Nayak; Emil M. Petriu; Wen-Ben Jone; Mehmet Sahinoglu (IEEE Trans. Instrum. Meas., 2007)

A Novel Technique for Input Vector Compression in System-on-Chip Testing. - Satyendra N. Biswas; Sunil R. Das; Mansour H. Assaf (ICIT, 2008)

Aliasing-free compaction revisited. - Sunil R. Das; Altaf Hossain; Satyendra Biswas; Emil M. Petriu (IET Circuits Devices Syst., 2008)

On a New Graph Theory Approach to Designing Zero-Aliasing Space Compressors for Built-In Self-Testing. - Sunil R. Das; Altaf Hossain; Satyendra Biswas; Emil M. Petriu; Mansour H. Assaf; Wen-Ben Jone; Mehmet Sahinoglu (IEEE Trans. Instrum. Meas., 2008)

Aliasing-Free Space Compaction in VLSI with Cascade of Two-Input OR/NOR Logic. - Altaf Hossain; Voicu Groza; Sunil R. Das (DELTA, 2011)

Compressed video watermarking technique. - Satyendra N. Biswas; Touhidul Hasan; Shuvashis DasGupta; Sunil R. Das; Voicu Groza; Emil M. Petriu; Mansour H. Assaf (I2MTC, 2013)

Data compression using mixed cascade of nonlinear logic. - Sunil R. Das; Danny L. Shaw; Satyendra N. Biswas; Mansour H. Assaf; Scott Morton; Irem Ozkarahan; Emil M. Petriu; Voicu Groza (I2MTC, 2013)

Design and implementation of high-performance master/slave memory controller with microcontroller bus architecture. - Shashisekhar Ramagundam; Sunil R. Das; Scott Morton; Satyendra N. Biswas; Voicu Groza; Mansour H. Assaf; Emil M. Petriu (I2MTC, 2014)

On System-on-Chip Testing Using Hybrid Test Vector Compression. - Satyendra N. Biswas; Sunil R. Das; Emil M. Petriu (IEEE Trans. Instrum. Meas., 2014)

Image processing based system for classification of vehicles for parking purposes. - Amit Krishan Kumar; Mansour H. Assaf; Sunil R. Das; Satyendra N. Biswas; Emil M. Petriu; Voicu Groza (I2MTC, 2015)

Designing elementary-tree space compressors using AND/NAND and XOR/XNOR combinations. - Nicholas A. Malan; Sunil R. Das; Satyendra N. Biswas; Mansour H. Assaf; Scott Morton; Emil M. Petriu; Voicu Groza (I2MTC, 2015)

A compact multispectral image capture unit for deployment on drones. - Ezekiel Bokolonga; Martin Hauhana; Nicholas Rollings; David Aitchison; Mansour H. Assaf; Sunil R. Das; Satyendra N. Biswas; Voicu Groza; Emil M. Petriu (I2MTC, 2016)

An algorithm for generating prime implicants. - Sunil R. Das; Abdullah-Al Amin; Satyendra N. Biswas; Mansour H. Assaf; Emil M. Petriu; Voicu Groza (I2MTC, 2016)

Short duration voice data speaker recognition system using novel fuzzy vector quantization algorithm. - Satyanand Singh; Mansour H. Assaf; Sunil R. Das; Satyendra N. Biswas; Emil M. Petriu; Voicu Groza (I2MTC, 2016)

Memristor-Based High-Speed Memory Cell With Stable Successive Read Operation. - Mohammad Nazmus Sakib; Rakibul Hassan; Satyendra N. Biswas; Sunil R. Das (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Face Identification Based on Discrete Wavelet Transform and Neural Networks. - Samrat Pundalik Khadilkar; Sunil R. Das; Mansour H. Assaf; Satyendra N. Biswas (Int. J. Image Graph., 2019)

An Optimized Tongue Drive System for Disabled Persons. - Komal Chand; Kavilash Chand; Rahul Kumar 006; Bibhya Sharma; Mansour H. Assaf; Sunil R. Das; Voicu Groza; Emil M. Petriu; Satyendra N. Biswas (I2MTC, 2021)

Epileptic Seizure Detection Using Convolution Neural Networks. - William Sukaria; James Malasa; Shiu Kumar; Rahul Kumar 006; Mansour H. Assaf; Voicu Groza; Emil M. Petriu; Sunil R. Das (MeMeA, 2022)