Area efficient current steering DAC using current tuning. - Sunil Rafeeque (APCCAS (1), 2002)

An on-chip DNL estimation and reconfiguration for improved linearity in current steering DAC. - Sunil Rafeeque; Vinita Vasudevan (ISCAS (1), 2004)

A Built-in-Self-Test Scheme for Digital to Analog Converters. - Sunil Rafeeque; Vinita Vasudevan (VLSI Design, 2004)

A Built-in-Self-Test Scheme for Segmented and Binary Weighted DACs. - Sunil Rafeeque; Vinita Vasudevan (J. Electron. Test., 2004)

A new technique for on-chip error estimation and reconfiguration of current-steering digital-to-analog converters. - Sunil Rafeeque; Vinita Vasudevan (IEEE Trans. Circuits Syst. I Regul. Pap., 2005)

A Novel Channel-Aware, Non-Sampling UART With Augmented Clock Frequency Resilience. - Timothy Simon Thomas; Arun Singh; Shyam Ramanathan; Sunil Rafeeque (IEEE Trans. Circuits Syst. II Express Briefs, 2024)