Circular LPC modeling and constant pitch transform for accurate speech analysis and high quality speech synthesis. - Sunil Shukla; Ali Erdem Ertan; Thomas P. Barnwell III (ICASSP, 2002)

A Fault Modeling Technique to Test Memory BIST Algorithms. - Raja Venkatesh; Sailesh Kumar; Joji Philip; Sunil Shukla (MTDT, 2002)

Single bit error correction implementation in CRC-16 on FPGA. - Sunil Shukla; Neil W. Bergmann (FPT, 2004)

QUKU: A Fast Run Time Reconfigurable Platform for Image Edge Detection. - Sunil Shukla; Neil W. Bergmann; Jürgen Becker 001 (ARC, 2006)

QUKU: A Coarse Grained Paradigm for FPGAs. - Sunil Shukla; Neil W. Bergmann; Jürgen Becker 001 (Dynamically Reconfigurable Architectures, 2006)

From Equation to VHDL: Using Rewriting Logic for Automated Function Generation. - Carlos Morra; M. Sackmann; Sunil Shukla; Jürgen Becker 001; Reiner W. Hartenstein (FPL, 2006)

QUKU: A Two-Level Reconfigurable Architecture. - Sunil Shukla; Neil W. Bergmann; Jürgen Becker 001 (ISVLSI, 2006)

Improving High Quality TTS using Circular Linear Prediction and Constant Pitch Transform. - Sunil Shukla; Thomas P. Barnwell III (ICASSP (4), 2007)

QUKU: A FPGA Based Flexible Coarse Grain Architecture Design Paradigm using Process Networks. - Sunil Shukla; Neil W. Bergmann; Jürgen Becker 001 (IPDPS, 2007)

Improving High Quality Concatenative Text-to-Speech Using the Circular Linear Prediction Model. - Sunil Shukla (2007)

A Web Server Based Edge Detector Implementation in FPGA. - Sunil Shukla; Neil W. Bergmann; Jürgen Becker 001 (ISVLSI, 2008)

QUKU: A Mixed Grain Dynamically Reconfigurable Architecture for High Performance Computing - Sunil Shukla (2008)

Improving intelligibility of synthesized speech in noise with emphasized prosody. - Sunil Shukla (ExLing, 2010)

FPGA-based combined architecture for stream categorization and intrusion detection. - Sunil Shukla; Rodric M. Rabbah; Martin Vorbach (MEMOCODE, 2010)

Virtualization of heterogeneous machines hardware description in a synthesizable object-oriented language. - Joshua S. Auerbach; David F. Bacon; Perry Cheng; Rodric M. Rabbah; Sunil Shukla (DAC, 2011)

A compiler and runtime for heterogeneous computing. - Joshua S. Auerbach; David F. Bacon; Ioana Burcea; Perry Cheng; Stephen J. Fink; Rodric M. Rabbah; Sunil Shukla (DAC, 2012)

The Liquid Metal IP bridge. - Perry Cheng; Stephen J. Fink; Rodric M. Rabbah; Sunil Shukla (ASP-DAC, 2013)

And then there were none: a stall-free real-time garbage collector for reconfigurable hardware. - David F. Bacon; Perry Cheng; Sunil Shukla (Commun. ACM, 2013)

FPGA Programming for the Masses. - David F. Bacon; Rodric M. Rabbah; Sunil Shukla (ACM Queue, 2013)

QUKU: A dual-layer reconfigurable architecture. - Neil W. Bergmann; Sunil Shukla; Jürgen Becker 001 (ACM Trans. Embed. Comput. Syst., 2013)

Parallel real-time garbage collection of multiple heaps in reconfigurable hardware. - David F. Bacon; Perry Cheng; Sunil Shukla (ISMM, 2014)

Cycle-Accurate Replay and Debugging of Running FPGA Systems. - Sunil Shukla; David F. Bacon (FCCM, 2015)

Growing a Software Language for Hardware Design. - Joshua S. Auerbach; David F. Bacon; Perry Cheng; Stephen J. Fink; Rodric M. Rabbah; Sunil Shukla (SNAPL, 2015)

Approximate computing: Challenges and opportunities. - Ankur Agrawal; Jungwook Choi; Kailash Gopalakrishnan; Suyog Gupta; Ravi Nair; Jinwook Oh; Daniel A. Prener; Sunil Shukla; Vijayalakshmi Srinivasan; Zehra Sura (ICRC, 2016)

Accelerator Design for Deep Learning Training: Extended Abstract: Invited. - Ankur Agrawal; Chia-Yu Chen; Jungwook Choi; Kailash Gopalakrishnan; Jinwook Oh; Sunil Shukla; Viji Srinivasan; Swagath Venkataramani; Wei Zhang 022 (DAC, 2017)

Across the Stack Opportunities for Deep Learning Acceleration. - Vijayalakshmi Srinivasan; Bruce M. Fleischer; Sunil Shukla; Matthew M. Ziegler; Joel Silberman; Jinwook Oh; Jungwook Choi; Silvia M. Mueller; Ankur Agrawal; Tina Babinsky; Nianzheng Cao; Chia-Yu Chen; et al. (ISLPED, 2018)

A Scalable Multi- TeraOPS Deep Learning Processor Core for AI Trainina and Inference. - Bruce M. Fleischer; Sunil Shukla; Matthew M. Ziegler; Joel Silberman; Jinwook Oh; Vijayalakshmi Srinivasan; Jungwook Choi; Silvia M. Mueller; Ankur Agrawal; Tina Babinsky; Nianzheng Cao; Chia-Yu Chen; et al. (VLSI Circuits, 2018)

A 3.0 TFLOPS 0.62V Scalable Processor Core for High Compute Utilization AI Training and Inference. - Jinwook Oh; Sae Kyu Lee; Mingu Kang; Matthew M. Ziegler; Joel Silberman; Ankur Agrawal; Swagath Venkataramani; Bruce M. Fleischer; Michael Guillorn; Jungwook Choi; Wei Wang 333; Silvia M. Mueller; et al. (VLSI Circuits, 2020)

Efficient AI System Design With Cross-Layer Approximate Computing. - Swagath Venkataramani; Xiao Sun 013; Naigang Wang; Chia-Yu Chen; Jungwook Choi; Mingu Kang; Ankur Agarwal; Jinwook Oh; Shubham Jain; Tina Babinsky; Nianzheng Cao; Thomas W. Fox; et al. (Proc. IEEE, 2020)

RaPiD: AI Accelerator for Ultra-low Precision Training and Inference. - Swagath Venkataramani; Vijayalakshmi Srinivasan; Wei Wang 333; Sanchari Sen; Jintao Zhang; Ankur Agrawal; Monodeep Kar; Shubham Jain; Alberto Mannari; Hoang Tran; Yulong Li; Eri Ogawa; et al. (ISCA, 2021)

A 7nm 4-Core AI Chip with 25.6TFLOPS Hybrid FP8 Training, 102.4TOPS INT4 Inference and Workload-Aware Throttling. - Ankur Agrawal; Sae Kyu Lee; Joel Silberman; Matthew M. Ziegler; Mingu Kang; Swagath Venkataramani; Nianzheng Cao; Bruce M. Fleischer; Michael Guillorn; Matt Cohen; Silvia M. Mueller; Jinwook Oh; et al. (ISSCC, 2021)

Sensor based Smart Plant Monitoring using IOT and Deep Learning: A Systematic Approach. - Sukhdeep Kaur; Kapil Joshi; Mudduluru Charan Teja; Ajay Singh 003; Amen A. Khabeer; Sunil Shukla (ICCCS, 2022)

A 7-nm Four-Core Mixed-Precision AI Chip With 26.2-TFLOPS Hybrid-FP8 Training, 104.9-TOPS INT4 Inference, and Workload-Aware Throttling. - Sae Kyu Lee; Ankur Agrawal; Joel Silberman; Matthew M. Ziegler; Mingu Kang; Swagath Venkataramani; Nianzheng Cao; Bruce M. Fleischer; Michael Guillorn; Matthew Cohen; Silvia M. Mueller; Jinwook Oh; et al. (IEEE J. Solid State Circuits, 2022)

D1: A 7nm ML Training Processor with Wave Clock Distribution. - Tim C. Fischer; Anantha Kumar Nivarti; Raghuvir Ramachandran; Ram Bharti; Derek Carson; Anton Lawrendra; Vineet Mudgal; Vivek Santhosh; Sunil Shukla; Te-Chen Tsai (ISSCC, 2023)

A Switched-Capacitor Integer Compute Unit with Decoupled Storage and Arithmetic for Cloud AI Inference in 5nm CMOS. - Ankur Agrawal; Monodeep Kar; Kyu-Hyoun Kim; Sergey V. Rylov; Jinwook Jung; Seiji Munetoh; Kohji Hosokawa; Xin Zhang 025; Bahman Hekmatshoartabari; Fabio Carta; Martin Cochet; Robert Casatuta; et al. (VLSI Technology and Circuits, 2023)