A Software-Hardware Co-Optimized Sense Amplifier for 2T1C Cell-based DRAM In-Memory-Computing. - Sunjoo Whang; Soyeon Um; Sangwoo Ha; Hoi-Jun Yoo (ISOCC, 2024)

A 32.65µm2 Spin/Area Large Scale Ising CIM with Progressive Circular Dataflow and Bi-directional eDRAM Cell Array. - Jingu Lee; Sangwoo Ha; Sunjoo Whang; Soyeon Kim; Sangjin Kim; Soyeon Um; Wooyoung Jo; Hoi-Jun Yoo (ISCAS, 2025)

A 62.8 TOPS/W FP-INT Digital Computing-in Memory Processor with Bit-Reordered Adder Tree and Low Active Hierarchical Accumulator. - Sunjoo Whang; Sangwoo Ha; Soyeon Um; Sangjin Kim; Hoi-Jun Yoo (ISCAS, 2025)